CA1315889C - Computer workstation with interrupt signaling arrangement - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

A computer workstation including a processor, one or more input/output units, such as disk devices or network interfaces, a program memory and a video memory which contains video information displayed on a video monitor. An arbitration circuit selects among the processor and input/output units for transfers to and from the program memory and video memory. A master control circuit controls timing of transfers to and from the program and video memories, and periodically enables video update transfers of video information from the video memory to video control circuits, which control the video monitor. While a video update is in progress, the master control circuit holds off other transfer request of the processor and input/output units with the memory. The program memory stores interrupt vectors. In response to interrupt requests from units which require interrupt service, the master control circuit interrupts the processor. When the processor acknowledges the interrupt, the master control circuit enables the transfer from the memory to the processor of the interrupt vector associated with the highest priority interrupt.

Description

li 3 ~

BAC~GROUND OF THE INVENTION

1. Field of th Invention The invention relates generally to the field o~ digital data processins systems, or computer systems, and more specifically to computer workstations.

2._3ackground Until recently, computer systems were large, expensive machines, generally too expensive to devote an entire computer system to one person. However, with the development of large and very large scale integrated circuit technology, which in turn provided the microprocessor, providing a computer system to one person has become cost effective. Personal com~uters and the more advanced computer workstations permit one person to have sole access to his or her computer for many kinds of activities, including word processing, accounting and financial planning, and computer aided design and engineering. In many cases, the personal computers and workstations are connected over a network to a larger minicomputer or -2- ~31~9 83-~70 mainframe which provides large scale data storage and data base management capabilities and manages such auxiliary equipment as printers and telecommunication interfaces.
These arrangements permit 5haring o~ information among users working on the personal computers and workstations. In addition, the larger computer may perform complex or lengthy arithmetic calculations, such as recalculating spreadsheets and processing of engineering simulations.

A computer workstation generally includes a processor, a memory, auxiliary storage such as disk storage, a keyboard for user data entry and a video display for displaying output to the user. In addition, i~ the workstation is to be used in a network, a network interface will also be included. The processor includes a microprocessor chip and may also include one or more auxiliary processor chips for processing special classes of instructions, most notably floating point instructions. The memory includes a read only portion (ROM) which generally includes the boot portion o the operating system, read/write random access memory (RAM) which is used for program instruction and data storage, including the remainder of the operating system, ~ g g~ ~3-470 ~3--and a video RAM which stores data depicting the image do be displayed on the video monitor.

When the workstation is initially turned on, the processor initially operates in response to bootstrap instructions ~rom the boot ROM, and enables the remainder o~
the operatin~ system and other programs and program data to be loaded into the ~hM from the disk storage devices.
During subsequent program execution, the processor may write data to be displayed into the video RAM. The network interface is also connected to the RAM ~o enable data from the network to be loaded therein or data to be retrieved therefrom for transmission over the network. Circuits for controlling the video display read the data out of the video RAM and in response to the data generate video signals which are coupled to the video display. Based on the video signals, the video display generates an image for the user.

The processor, disk storage devices, network interface and video control circuits are all connected to write data to or retrieve data from one or more portions of the memory.
(User input through the keyboard is typically handled as a interrupt serviced by the processor rather than as a direct transfer to memory.) All portions of the memory, that is, ~ 3 ~
~3-~70 _~_ the boot RO~, the RAM and the video RAM typically occupy a single address spa~e, that is, the addresses of the locations in the boot ROM, RAM and video R~M do no~ overlap.
In addition, the disk storage devices and network interface typically include control and status registers which also occupy a portion of the same address space. ThuS, if the processor, for example, wishes to perorm a transfer with any storage loca~ion in the boot ROM, R~M, video RAM or any of the control and sta~us registers in the disk devices or network interface, the address transmitted by the processor during the transfer completely identifies the location.

The video image displayed by the video display unit is in "real time", that is, ~ne generation of the image cannot be delayed without disrupting the image as seen by the viewer. Accordingly, the video control circuitry must be able to retrieve data from the v deo RAM in a timely manner~
~owever, access to the memory can be impeded by memory requests from the processor, disk devices or network interface. Typically, a workstation includes an arbitration mechanism which arbitrates memory requests among the various devices, that is, the processor, video control circuitry, network interface and disk storage devices, which may be ~3~3~ 83-470 _5_ requesting access to memory. HowevPr, this requires a complex mechanism to ensure that the video control circuitry has access to the m mory, and specifically the video RAM in a timely manner to ensure that the image on the video display is not disrupted.

In most digital data processing systems, devices, most notably input/output devices such as keyboards, disk storage systems, network interaces, and video circuits often need to communicate with the processor to request servicing by the processor. In some systems, the processor periodically polls the various devices to determine if they need assistance. In others, the devices interrupt the processor when they need assistance. Usually, an interrupt is signalled by the units transmitting a signal over one or several signal lines. Ater receiving the interrupt, the processor may begin processing the interrupt by acknowledging it. In this, it obtains an interrupt vector from a unit requesting interrupt service. The in~errupting units maintain their interrupt vectors~ In response to an interrupt acknowledgement by the processor, a unit requesting interrupt service transfers its interrupt vector to the processor. If more than one unit is requesting - 6 ~ ~ 3 ~ 36Qgo~

interrupt service, circuitry is provided in the system to select one of the units to transfer its interrupt vector -to the process-or SUMMARY OF THE INVE~TION
The invention provides a new and improved compu-ter sys-tem which simplifies the handling of interrupt requests from the various devices comprising the computer.
In brief summary, the new computer system includes a processor and one or more input/output devices, such as a disk device, a network interface, a serial communica-tions port and the like, and a common memory, including a portion which contains system control information such as interrupt vectors, and a master control circuit for controlling data transfer transactions among the various devices~ When a device wishes to interrupt the pro-cessor, it generates an interrupt request. The master control circuit accumulates the interrupt requests from all the devices and transmits a single interrupt request to the processor. ~1hen the processor generates an interrupt acknowledgement transaction, the master control circuit enables the common memory to transfer an interrupt vector to the processor.
The invention obviates the need for the various devices in the computer system to maintain their own individual interrupt vectors, since all of the vectors are maintained in the common memory. It also permits simplification of the devices' inter-faces, since the master control circuit is the only device in the system which needs to be able to identify an interrupt acknow-~3 13~8~9 - 7 - 69gO~ 4 ledgement transaction. In addition, the inven-tion simplifies changing interrupt vectors, since they are all located in a single device, namely, the common memory.
The invention may be summarized as a digital computer system including a system bus and a plurality of devices connected to the bus, said system comprising:
A. a processor Eor performing data transfer and inter-rupt servicing operations speci-fied in interrupt service routines, said processor including interrupt acknowledging means for generating an interrupt acknowledge signal in response to an interrupt request signal;
B. memory means for storing data and interrupt service routines;
C. interrupt generating means in each device for genera-ting interrupts when the device requires processor attention; and D. control circuit means for: -i. accumulating the interrupts generated by said interrupt generating means, ii. prioriti~ing the accumulated interrupts, and iii. signalling a single interrupt request to said processor;
said processor sending an interrupt acknowledge signal to said control circuit means to acknowledge the interrupt request and said control circuit means, in response to the interrupt acknow-~ ~.

6g904-144 ledge signal, directing sald processor to the location in the memory means which contains the interrupt service routine associated with the then highest priority accumulated interrupt.

BRIEF DE'SCRIPTION OF THE DRAWINGS

. _ This invention i5 pointed out with parti.cularity in the appended claims. The above and further advantages of this invention may be better understood by referring to the follow.ing description taken in conjunction with the accompanying drawings, in which:
Fig. 1 depicts a general block diagram of a computer workstation constructed in accordance with the invention;

7a Fig. 2 depicts a functional block diagram o~ a master control circuit in the computer workstation depicted in Fig. 1 DE~ILED D~SCRIPTION OF AN ILLUSTRATIVE EMBODIMENT

A computer workstation constructed in accordance with the invention is shown, in general block diagram form, in Fig. 1. With reference to Fig. 1, the workstation include~
a processor 10 including a central processor unit (CPU) 11 and floating point accelerato~ processor 12 which transfer addresses and data, including such in~ormation as proyram instructions and program data, with other units in the system through a buffer 13. The floating point accelerator processor 12 is provided to accelerate processing of floating point instructions. The processor 10 generates and transmits a free-running S~S CLR system clock signal to synchronize events in the workstation. In one embodiment, the processor 10 operates in synchronism with a multiple phase clock, with the ticks of the SYS CLK system clock signal (that i5, the successive leading edges of the SYS CLK
system clock signal) defining the ticks of the successive phases of the processor's multiple phase clock.

- 9- ~3~8~9g4-144 The workstation also includes a read/wri-te random access memory 20 containing a plurality of addressable storage locations for storing variable program instructions and data. A read only memory 21, which also contains a plurality of addre~sable storaye locations, stores fixed program instructions, including a boot-strap program and selected portions of the operating system such as service routines used in servicing interrupt request from, for example, input/output devices such as one or more disk devices 23 or a network interface 24 which may be included in the system.
The read only memory 21 also stores, at predetermined locations, a plurality of interrupt vectors 14. Each interrupt vector identi-fies the location, in either random access memory 20 or read only memory 21, of an interrupt service routine for servicing an inter-rupt request from units requiring interrupt service from the pro-cessor 10.
As is conventional, the system may also include o-ther input/output devices, such as serial or parallel communications devices (not shown) which transfer information to or from the network and to printers for providing a hard copy output. Trans-fers to and B

~ 3-470 from these devices are performed in a slmllar manner as transfers to and from the ~isk devices 23 and network interface 24, and so these additional devices will not be described further here.

In addition, a read/write random access memory serves as a video memory 22 to store, also in addressable storage locations, video data detailing an image to be displayed on a video monitor (not shown). In one specific embodiment, the video memory 22 contains a ~bit-mapped" representation of the image to be displayed on the video display, that i5, the data bits stored in the addressable locations in the video memory 22 have a direct correspondence to the individual picture elements (pixels) displayed.

As described below, the processor 10 can read the informat on stored in addressed locations in the random access memory 20, read only memory 21 and through a driver 27, video memory 22, and i~ can also write information to addressed locations in the random access memory 20 and, video memory 22.

In addition, periodically the information stored in a plurality of sequential locations in the video memory 22 is ~c~ 3_470 transferred in parallel ~rm at one time to a shift register 25 to update its contents. Shift register ~5 shi~ts its contents ou~ in serial form to conventional video display control circuits (not shown) in response to a VSR SCLK video shift register shift clock slgnal from the video display control circuits. In response to ~he contents of the video shift register 25, the video display control circuits generate in a known manner video signals which control the video monitor and are displayed as an image.

It will be appreciated that the driver 27 serves to isolate the data out terminals of video memory 22 and, more particularly, khe data in ter~inals of video shift register 25 from the data/address lines 15, since, as will be described in more detail below, the data/address lines 15 may have signals thereon during a video shift register update operation.

The processor 10 can also read information stored in control and status registers (not shown) in the disk devices 23 and network interface 24 and transfer information to such registers to control the respective units. The control and status registers are, like the storage locations in the randcm access memory 20, read only memory 21 and video ~ 3~ 3-470 memory 22, identified by addresses. In response to selected conditions, such as the detection of an error or the completion of a disk read or write operation the disk devices 23 may assert a DIS~ INT REQ disk interrupt request signal. In addition, at the end of a network transfer, the network interface 24 may assert a NET INT ~EQ networ~
interrupt request signal. The disk devices 23 may also assert the DISR INT REQ disk interrupt request signal during a disk storage operation to request the processor to transfer data to it from the memory 20, or to transfer data from it to the memory 20.

In addition, during the video monitor's vertical blanking interval, during which the electron beam is returned from the bottom of the video screen to the top of the video screen, the proc0ssor 10 is interrupted by a VERT
~LK vertical blank interrupt request signal. In response to the VERT BL~ vertical blank interrupt request signal, the processor 10 performs certain housekeeping operations as described below. The interrupt controller 14 receives the DISK INT REQ disk interrupt request, NET INT REQ network interrupt request, and VERT BLR vertical blank interrupt ~3~S~ 83-470 request signals and at an appropriate time interrupts the CPU 1 1 .

In addition, other units such as the aforementioned serial and parallel communications devices (not shown~
typically also generate interrupt request signals to permit the processor 10 to per~orm selected operations therewith.
The operations normally performed by a processor 10 for such devices are well known in the art and will not be described in detail.

The buffer 13 in processor 10 buffers transmissions of data and address information between the CPU 11 or floating point accelerator processor 12 and a set of data/address lines (~AL) lS. The data/address lines 15 are used to transfer data and address information from processor 10 during a write operation with other units in the system, that is, during a transmission to one of the memories 20 through 22, or to a control or status register in disk devices 23 or network interface 24. In addition, the data/address lines 15 are used during a read operation to return read data from the storage location or register identified by an address which is also transmitted by processor 10 over the data/address lines 15. In one ~ 3 ~

embodiment, thirty-six data/address lines 15 carry, in parallel, thirty-two information signals, which comprise four eight-bit bytes of information, and four parity signals (one associated with each byte) which are used in error detection.

As is typical, the network interface 24 is a direct memory access (DMA) device. Tha~ is, network interface 24 retrieves data directly from, in particular, random access memory 20 for transmission over a network (not shown). In addition, network interface 24 transmits data received from the network directly to random access memory 20 for storaqe therein.

The disk devices 23 may also comprise a direct memory access device, but in the embodiment described herein lt is not. Instead, the processor 10 initiates the transfer of data to or from the disk devices 23 in response to an interrupt therefrom.

To initiate a DMA operation, the network interface 24 asserts an NET DMR network direct memory request signal. In response a DMA control circuit 26 asserts a DMR direct memory request signal which is transmitted to the processor ~ 31 ~
- 15 - ~9gO~-144 10. When the processor 10 is to grant a direct memory operation, it asserts a DMG direct ~emory grant signal, which is received by the DMA control circuit 26. The DMA control circuit then asserts the NET DMG network direct memory grant signal which enables the network interface 24 to engage in a DMA operation. If other devices are connected into the system which transfer da-ta wi-th memory 20 in a direct memory access manner, the DMA control circuit also receives device direct memory request signals there-from and transfers device direct memory grant signals thereto. If more than one request signal is asserted when the processor 10 asserts the DMG direct memory grant signal, the DMA control circuit 26 asserts one of the device direct memory grant signals based on a predetermined priority in a conventional manner.
Like the processor 10, during a DMA operation the network interface ~4 provides addresses to identify the location from which data is being retrieved or into which data is being written. DMA operations occur under control of control informa-tion in the control registers in the respective units which is provided by processor 10. The DMA operations are carried out without intervention by processor 10. As is conventional, at the end of a transfer operation, the unit asserts its NET INT REQ
network interrupt request signal to request interrupt service by the processor 10.
In accordance with the invention, a master control circuit 30 controls the timing of transfers initiated by ~' ;

- l6 -- 69gO4--144 processor lO with random access memory 20, read only memory 21 and video memory 22, and the control and status registers of disk devices 23 and network interface 24 over data/address lines 15.
In addition, the master control circuit 30 con-trols refresh of the random access memory 20 and video memory 22 and the trans-fer of video informa-tion from the video memory 22 to the shift register 25 during a video shift register update operation. The master control circuit 30 further controls the timings of DMA transfers between the network interface 24 and random access memory 20. If a video shift register update operation is enabled, the master control circuit 30 holds off other operations which may be initia-ted by the processor lO or network interface 24 until the video shift register update operation and subsequent refresh operations have completed. After the video shift register update operation has been completed, B

.

131~9 B3-470 the master control circuit 30 enables other operations with memory to proceed from the appropriate cycl~ o the SYS CLK
system timing signal.

Finally, the master control circuit receives interrupt request signals, such as the DISK INT REQ disk interrupt request, NET INT REQ network interrupt request and VID INT
REQ video interrupt request signals, and other interrupt request signals rom other devices (not shown~ which may be in the system, and`transmits a single INT REQ interrupt request signal to the processor 10. In response to a later interrupt acknowledge transaction, as described below, from the processor 10, the master control circuit enables the transfer of an interrupt vector from th~ read only memory 21 to the processor 10. The master control circuit 30 establishes an interrupt priority among the various units which generate interrupt request signals, and if more than one unit is asserting an interrupt request signal when the processor 10 initiates an interrupt acknowledge transaction, the master control circuit 30 enables the transfer of the interrupt vector associated with the unit having the highest priority whose interrupt request signal is asserted.

~ ~3~$~
-lB-- The processor 10 or network interface 24, to initiate a transfer with a memory unit, that is, either the random access memory 20, read only memory 21, or video memory 22, first places address signals on data/address lines 15 and asserts an AS address strobe signal and an encoded CYC SEL
cycle select signal identifying a write operation if the operation is a write operation, that is, if data is to be stored in the location identified by the address. If the processor 10 is the initiating unit, ~his occurs in synchronism with a selected phase of the processor's internal multiple phase clock. If the operation is A read operation, in which data is to be retrieved from the location identified by the address, the CYC SEL cycle select signal is encoded to identify a read opera~ion. Finally, if the operation is an interrupt acknowledge operation, th~
processor 10, which is the only unit which initiates this type of operation, transmits an encoded CYC SEL cycle select signal which identifies the operation as an interrupt acknowledge operation. In addition, if the processor 10 is the initiating unit, it transmits a DT data type signal to identify the number of bytes being transferred during a write operation or being retrieved during a read operation.

~3-~70 In response to the assertion of the AS address strobe signal, ~he master control circuit 30 latches the address signals on data/address lines 15, the encoded CYC SEL cycle select signal and the DT data type signal. ~ predetermined time later, the address signals are removed from the data/address lines 15. If the operation is a write operation, the data to be written is then placed on the data/address lines 15 and the DS data strobe siqnal is asserted. If the operation is a read operation or an interrupt acknowledge operation, the DS data strobe signal is asserted to indicate that the unit which initiated the operation, that is, either the processor 10 (in the case of a read operation or an interrupt acknowledge operation~ or the network interface 24 (in the case of a read operation) which transmi~ted the address signals and CYC SEL cycle select signal, is ready to receive the data or interrupt vector.

After receiving the address signals from the data/address lines 15, if the operation is a read operation or a write operation, the master control circuit 30 decodes the ~ddress to determine whether the operation is a transfer with one of the memory units 20, 21 or 22. If it is, and if ~ g~ ~3-470 no update of the video fihift register 25 or refresh operation is taking place, the master control circult 30 transmit6 the addre~s received from the data/addre6s line6 15 a~ MEM ADRS memory addre6s signals over line6 31 to the address input terminals of memory units 20, 21 and 22.

As is typical in random access type memorie~, the random access memory 20 and video memory 22 require sequential transmission of row address signals accompanied by a row address 6trobe ~ignal, and column addre6s sign~l~
accompanied by a column address ~trobe signal, along with a write enable signal to identi~y the operation. Thus, if the transfer i~ with the random access memory 20, the master control circuit 30 transmits the row address signals as MEM
ADRS memory address signals over lines 31, asserts a RAM WE
random access memory write enable signal and a RAM RAS
random access memory row address strobe signal which enables the random access memory 20 to latch the row addre~s on lines 31 and the RAM W~ random access memory write enable signal.

Thereafter, the master control circuit 30 remove~ the row address signals from lines 31 and transmits the column address as t.:-.e M~M ADRS memory address signals over lines 31 ~ 3 ~

and a~sert~ a RAM CAS random access memory column addres6 strobe signal. In particular, the RAM ~*~- random access memory column address strobe signal is a signal which is encoded in response to the DT data type signal to enable sufficient locations in the random acce6s memory 20 to participate in the operation to store or retrieve the amount of data identified by the DT data type signal.

If the operation is a write operation, by this time, the write data is on data/address lines 15, and so the random access memory 20 stores the write data in the addressed location. Similarly, if the operation is a read operation, by this time the initiating unit is ready to receive the data from the identified location. The random access memory 20 then asserts a RAM RDY random access memory ready signal if no error has occurr~d, or a RAM ERR random access memory error signal if an error has occurred. An error may be indicated, for example, if the random access memory 20 detects a parity error in data received from data/address lines 15 if the operation is a write operation or retrieved from the location identified by the address if the operation is a read operation.

1 3 ~ 3 9 - 22 -- 6990~-144 If no error is detected by random access memory 20, when the data has been loaded into the addressed location during a write operation, or when the read data is on data/address lines 15, the master control circuit 30 asserts the RDY ready signal.
When the RDY ready signal has been asserted, the unit initiating the transfer latches the data on the data/address lines 15 if the transfer is a read operation. The initiating unit then negates the DS data strobe signal, in response to which the master control circuit 30 negates the RDY ready signal, and negates -the AS
address strobe signal to terminate the transfer.
During a transfer, if the master control circuit 30 detects a parity error in the address signals which it receives ~rom data/address lines 15, it does not engage in any transmission of MEM ADRS memory address signals over lines 31, or RAM RAS
random access memory row address strobe or RAM CAS random access memory column address strobe signals to the random access memory 20. Instead, the master control circuit 30, upon receipt of the asserted DS data strobe signal, asserts an ERR error signal.

A similar sequence occurs when address signals transmitted over the data/address lines 15 identi~y a location in the video memory 2~. In that case, instead oP
RAM RAS random access memory row address strobe, RAM CAS
random access memory column addre6s strobe and RAM WE random access memory write enable signals, the master control circuit 30 transmits VRAS video row address strobe, VCAS
video column address strobe and V WE video write enable ~ignals. In addition, instead of the RAM RDY random access memory ready and RAM ~RR random access memory error signals, the master control circuit 30 receives V RDY video ready and V ERR video error signals in response to the transfzr.

Read only memory 21 requires only a single set of address signals transmitted over lines 31 along with a ROM
EN read only memory enabling signal to initiate a transfer.
If the address signals identify a location in the read only memory 21, the master control circuit 30 transmits the address signals over lines 31 and asserts the ROM EN
enabling signal. In response, the read only memory 21 transmits the contents of the addressed location through its data out terminals and asserts either the ROM RDY or ROM ERR
read only memory ready or error signals. In response to the 9 ~3-~170 receipt of the ROM ~DY or ROM ERR read only memory ready or error signal, the master control circuit 30 asserts the corresponding RDY ready or ERR error signal.

The interrupt acknowledge operation is similar to a read operation described above, except that the processor 10 does not transmit address signals over data/address lines 15. Instead, the master control circuit 30 generates address signals which identify the location in read only memory 21 which stores the interrup~ vector associated w~th the unit in the system with the highest interrupt priority.
The master control unit 30 enables ~he read only memory 21 to transmit the interrupt vector over the data/address lines 15 with the same timing, with respect to the DS data strobe signal from processor 10, with which it enables transfers of data from memories 20 through 22 during a read operation.

As noted above, the processor 10 may also perorm a read or write operation with control and status registers in disk devices 23 and network interface 24. In that case, the master control circuit 30 does not transmit address signals over lines 31; instead the disk devices 23 and network interface 24 receive the address signals and, if the operation is a write operation, data signals directl~ from ~ ~3~ 3-~70 the data/address lines 15. In addition, since the contents of an entire con~rol and status register will alway~ be loaded or retrieved, the DT data ~ype signal is not u6ed.
The master control circuit 30 also receives the address signals, checks parity and determines wh~ther they identify the disk devices 23 or network interface 24. If they do, it asserts a DISK AS disk address strobe or a NET AS network address strobe signal, which are received by the disk devices 23 and network interface 24, respectively.

In response to the DISK AS disk address strobe signal the disk devices 23 latch the address on the data/address B lines 15 and the CYC SEL cycle select signal and i~ ~ ~ s-the control and status register to engage in the transfer operation. Similarly, in response to the NET ~S network address strobe signal, the network interface 24 latches the address on the data/address lines 15 and the CYC SEL cycle select signal and identifies the cor.trol and status register therein to engage in the transfer operation.

Thereafter, if the operation is a write operation, the processor 10 places the data signals on data/address lines 15 and asserts the ~S data s~robe signal. In response, the master control circuit 30 asserts the DISX DS disk data strobe if the DISR AS disk address strobe signal was ~ 3 1 ~ 3-470 previously asserted or the NET DS ~etwork data strobe ~ignal if the NET AS network address strobe signal was previously as~erted. If the DISK DS disk data strobe signal is asserted, the disk devices 23 receives the data from the data/addre6s lines lS if the operation is a write operation and if there is no parity error loads it into the control and status register identified by the previously latched address. If the operation is a read operation, the disk devices 23 retrieve the contents of the control and status register identified by the previously latched addres6 and places it on the data/address lines 15. Thereater, the disk devices 23 asserts a DISK RDY disk ready signal if there was no error, or a ~ISK ERR disk error siqnal if an error had occurred.

In response to the assertion of a DISK RDY disk ready signal or the DISK ERR disk error signal, the master control circuit 30 asserts the RDY ready or ERR error signal, respectively, to indicate to the processor 10 completion of the operation. In response, the processor 10 negates the DS
data strobe and AS address strobe signals. The master control circuit 30 then negates the DISK DS disk data strobe and DISK AS disk address strobe signals.

~ 3~470 Similar operations occur in connection with transfers to and from control and status registers in the network interface 24. If a transfer from the processor 10 is to or from a control or status register in the master control circuit 30, the ~aster control circuit 30 performs the requested transfer directly.

As described above, the master control circuit 30 controls transfers of video information from the video memory 22 to the video shift register 25. When the content6 of the video shift register 25 have been shifted out to the video display circuitry (not shown), new video data must be transferred from the video memory 22 to the video shift register 25. This updates the video shift register 25 with additional video information which is shifted out to generate the image displayed on the monitor.

The video memory 22 and video shift register 25 are organized so that a row address and a column address of zero (that is, a column address in which all signals transmitted to the video memory 22 are negated) enables ~he video memory 22 to transmit sufficient information to fill video shift register 25. ~he master control circuit 30 transmits the row address as MEM ADRS memory address signals over the bus - ~3~ 83-470 ~ -28~
31. ~ short time later, to allow the MEM ~DRS memory address signals to settle, the master control circuit 30 asserts the VRAS video row address strobe signal to allow the video memory 22 to receive the MEM ADRS memory address signals. The master control circuit 30 then removes the row address signals, places negated MEM ADRS memory address signals on lines 31 as the column address and asserts the VCAS video column address strobe signal.

In response to the MEM ADRS ~emory address signals, the contents of the identified row of storage locations in the video memory 22 are transmitted in parallel as VID OUT video out signals through the video memory's data out terminals and received at the video shift register~s data in terminals. A short time later, to allow the VID OUT video out signals to settle, the master control circuit 30 asserts a VSR LD video shift register load signal, enabling the video shift register 25 to load the VID OUT video out signals. The video display circuitry, which controls the video monitor ~also not shown), generates a VSR SCLK video shift register shift clock signal to enable the data in the video shift register 25 to be shifted out in serial form.
The video display circuitry uses the digital serial data ~3~ 83-from the video shift regi6ter 25 to generate analog signal~
defining ~he image displayed on the video monitor.

Immediately following an update of the video shi~t regi6ter 25, the master cont~ol circuit 30 initiates a series of successive refresh operations in random access memory 20. To accomplish this, the master control circuit 30 transmits MEM ADRS memory address signals over lines 31 to identify the row to be refreshed. ~fter the MEM ADRS
memory address signals have settled, ~he master control circuit 30 asserts the RAM RAS random access memory row address strobe signal which enables refresh ~o occur.

During a video shift register update operation or a refresh operation, the processor 10, disk devices 23 or network interface 24 may initiate a trans~er operation over data/address lines 15. The master control circuit 30 latches the address signals which are transmi~ted over data/address lines 15 and the CYC SEL cycle select signal, but does not otherwise enable the operation to continue.
Following the refresh operation, the master control circuit 30 proceeds with the operation. This permits the video shift register update operation and refresh operation to ~3~ 3-470 always have priority over other operation~ with respect to random access me~ory 20 and video memory 22.

The master control circui~ 30 will be descri~ed in more detail in connection with Fig. 2, which depicts a functional block diagram of the master control circuit 30. With reference to Fig. 2, the master control circuit 30 has four sources of addresses which it may couple over address lines 31 as MEM ADRS memory address signals. In particular, the master control circuit 30 may receive address s~gnals over data/address lines 15, which address signals are latched in an address buffer 50 in response to an ~DRS LTH address latch signal from a control circuit 51. The control circuit 51 asserts the AD~S LTH address latch signal in response to the AS address strobe signal. At the same time that the address buffer 50 latches khe address signals on data/address lines 15, a latch 83 latches the CYC SEL cycle select signals which identify a type of operation. The latch 83 provides LTH CYC SEL latched cycle select signals, which are coupled to the control circuit 51.

A second source of address signals is a video address counter 52, which generates VID ADRS video address signals which are used during a video shift register update ~ 3 ~

operation. A third 60urce~ of addresses is a refresh addre~s counter 53/~generates REF ADRS refresh addrefis signals used during refresh operations which follow video shift register update operations. In one specific embodiment, six refresh operations follow each video ~hift regi~ter update operation. In addition, since video shift register operations in connection with video memory 22 are performed sufficiently often that refresh of the video memory 22 i5 not required, refresh operations are only performed in connection with the random access memory 20.

Finally, a fourth source of addresses is an interrupt address circuit 80, which provides an address of an interrupt vector during an interrupt acknowledge operation.

In one embodiment, the memory address lines 31 carry eight MEM ADRS (7:0) memory address signals in parallel, and the data/address lines 15 may carry as many as thirty two address signals in parallel. The address buffer 50 is divided into a low order portion 54 and an intermediate portion 55, both of which store signals which may be used to address the memories 20, 21 and 22 during a memory operation, and a high order portion 56 which latches signals ~ ~ 3 1 ~ 83-~70 ~ 32 which identify a particular devic~ in the gystem depicted in Fig. 1.

The contents of the high order portion 56 of th~ .
addre~s buffer 50 are coupled, as DAL DEV SEL data/address lines device select signals, to a decoder 57. In response to the DAL DEV SEL data/address lines device select signals, B the decoder 57 asserts a~ RAM EN random access memory enable signal if the contents of the address buffer 56 identify a location in random access memory 20.

In addition, the decoder 57 asserts a~ROM EN read only memory enable signal if the contents of the address buffer identify a location in read only memory 21 and a VRAM EN
video memory enable signal if the contents of the address buffer 50 identify a location in video memory 22.
Similarly, the decoder 57 asserts a DIS~ EN disk enable or NET EN network enable signal if the contents of the address buffer 50 identify a location in disk devices 23 or network interface 24, respectively.

Finally, the decoder 57 asserts an MCC EN master control circuit enable signal if a control or status register in the master control circuit 30 is addressed. One ~ 3-470 such register, namely, an ~ffset regi5ter fiO, i6 depicted in F~g. 2. The offset register 60 receives a value which is loaded into the video address counter 52 when the counter counts out. The value in the video address counter is an offset into the video memory's address space used by the processor 10. The con~ents of the offset register 60 may be updated in response to a VID LD video load signal from control circuit 51 during the monitor's vertical blanking interval, enabled during servicing by processor 10 of the vertical blanking interrupt as described above.

The interrupt address circuit 80 includes an interrupt base address reyister 81 which s~ores the base address of the interrupt vPctors in read only memory 21 (Fig. 1~ and a priority encoder 82. The priority encoder receives the interrupt request signals from the devices which may request interrupt service, which signals are identified in Fiq. 2 as INT RE2 (7:0) interrupt request signals (that is, eight INT
REQ interrupt request signals) and generates b~ three INT
ADRS ~2:0) interrupt address signals. The register 81 transmits INT BASE interrupt base signals which, in turn, comprise high order address bits which are used during an interrupt acknowledge operation. The priority encoder 82 ~ 3 ~

provides INT ADRS (2:0) interrupt address signals which comprise three low order address bits which are concatenated onto the IN~ ~AS~ interrupt base signals to provide INT ACR
ADRS interrupt acknowledge address signals which are used during an interrupt acknowledge operation to identify the address of the location in read only memory 21 of th~
interrupt vec~or to be returned.

The contents of portions 55 and 54 of the address buffer 50 are transmitted as DAL ADRS HI data/address lines address high-order portion and DAL ADRS LO data/address lines address low-order portion signals, respectfully, to two sets of inpu~ terminals of a multiplexer 61. In addition, the outputs of the video address counter 52 and refresh address counter 53 are transmitted as VID ADRS video address and REF ADRS refresh address signals, respectively, to two other sets of input terminals of multiplexer 61. The INT ACK ADRS interrupt acknowledge address signals are also coupled to a set of input terminals of multiplexer 61.
Multiplexer 61 determines, in response to ADRS SEL address select signals at its select input terminals, the signals to be coupled onto lines 31 as MEM ADRS memory address signals.
The multiplexer 61 transmits the signals at the input ~ 3~ ~5 ~ 83-470 terminal identified by the AD~S SEL ~ignals in response to an asserted ADRS OUT EN address out enable signal, which is received at an output enable terminal from the control circuit 51. The ADRS SEL address select signals are also provided by control circuit 51.

If the operation is a read or write operation, as defined by the LTH CYC SEL latched cycle select signal from latch 83~ ~he control circuit 51 also generates the appropriate RAM WE random access memory write enable signal, V WE video random access memory write enable signal, DISR
WRT disk devices write enable signal, or NET WRT network interface write enable siqnal, depending on the condition of the RAM EN random access memory enabling signal, ROM EN read only memory enabling signal, VRAM video random access memory enabling signal, DISK EN d-.sk devices enabling signal, or NET EN network enabling signal from decoder 57. In addition, the control circuit 51 generates the DISK AS disk address strobe, DISR DS disk data strobe, NET AS network address strobe, NET DS network data strobe, RAM RAS and RAM
CAS random access memory row and column address strobe, VRAM
RAS and VRAM CAS video memory row and column address strobe signals. All of these signals are collectively identified ~ 3 ~

in Fig. 2 as DISK, NET, MEM CTRL SIG disk, network and memory control siqnalE to enable the operations with those devices as described above. Similarly, the control circuit 51 responds to the various DISK ERR, NET E~R, RAM ERR, ROM
ERR and VRAM ER~ error and DISR RDY, NET RDY, RA~ RDY, ROM
RDY and VRAM RDY ready signals~ which are collectively iden~ified as DISK, NET, MEM RESPONSE SIG disk, network and memory response signals, and generates the RDY ready and ERR
error signals in response thereto.

On the other hand, if the operation is an interrupt acknowledge operation, the control circuit 51 generates ADRS
SEL address select signals which enable the multiplexer 61 to transmit the INT AC~ ADRS interrupt acknowledge address signals as MEM ADRS memory address signals over lines 31.
The control circuit 51 also asserts a ROM EN read only memory enable signal which is coupled to read only memory 21 to enable it to couple the interrupt vector stored at the location identified by the INT AC~ ADRS interrupt acknowledge address signals. At the appropriate time, the control circuit 51 asserts the RDY ready or ERR error signal for transfer to the processor 10.

~ 3 ~ B3-470 The ma6ter control circuit 30 also includes a video timer 62 which periodically asserts a VI~ VPD video update signal to time updating of the video shi f t r~gister 25. The VID UPD video updats signal i5 coupled to a synchronizing flip-flop 63 which synchronizes the VID UPD video update signal to the S~s CL~ system clock signal. Since a HOLD
signal is not a6serted, an inverter 71 Pnables one input of an AND gate 70 to pass the SYS C~K system cloc~ signal from the processor 10 as SYNC CLR synchronlzing clock signal6 to control two synchronizing flip-flops 63 and 68. On the next tic~ of the SYS CLK system clock signal (that is, when it is next asserted) after timer 62 asserts the VID UPD video update signal, flip-flop 63 latches ~he asserted VID UPD
video update signal from timer 62 and generates an asserted VID UPD SYNC video update synchronized signal. The asserted VID UPD SYNC video update synchronized signal enables one input of an AND gate 64.

If the AS address strobe signal is in the asserted condition, indicating that a previously enabled operation is in progress, an inverter 65 disables one input of an AND
gate 66. Since the HOLD signal is negated, an inverter 67 enables the second input of the AND gate 66. When the AS

~ 3 ~

address ~trobe 6ignal is negated at the end of the previously enabled operation, inverter 65 enables the second input of AND gate 66, which, in turn, energizes the AND gate 66. This, in turn, enables the s~cond input of AND gate 64, thereby energizing it.

The energized AND gate 64 enables the data input terminal of flip-flop 68. ~t thP next tick of the sYs CLK
system clock signal, the flip-flop is set, which assert6 the HOLD s i gnal.

The HOLD signal is coupled to control circuit 51. When the HOLD signal is asserted, the control circuit is enabled to generate the signals described above to perform the video shift register update operation, followed by the refresh operations. In particular, the control circuit 51 initially generates ~DRS SEL address select signals and asserts the ADRS OU~ EN address out enable signal to enable the video address counter 52 to couple the VID ADRS video address signals from the video address counter 52 onto lines 31 as the MEM ADRS memory address signals. A selected time later, after the MEM ADRS memory address signals have had a chance to settle, the control circuit S1 asserts the VRAS video row address strobe signal.

13~5~3~9 ~3-470 A selected time later the con~rol cLrcuit 51 enables the multiplexer 61 to transmit MEM ADRS memory address signals of all zeros by negating the AD~S OUT EN address out enable signal. A selected time later, after these MEM ADRS
memory address signals have settl~d, the control circuit 51 asserts the VCAS video column address strobe signal. In response, the video memory 22 transmits VID OUT signals sufficient to fill video shift register 25, and the control circuit 51 asserts the VSR LD video shift register load signal to enable the video shift register 25 to load the VID
OUT signals. The con~rol circuit 51 then negates the VRAS
and VCAS video row and column address strobe signals and asserts a VID INCR video incremen~ signal which enables the video address counter 52 to increment.

Thereafter, the control circuit 51 enables a succession of refresh operations to occur in random access memory 20.
In particular, the control circuit 51 generates ADRS SEL
address select signals and asserts the ~DRS OUT EN address out enable signal which enable the multiplexer 61 to couple the REF ADRS refresh address signals f Eom refresh address counter 53 onto lines 31 as the MEM ADRS memory address signals. A selected time later, after the M~M ADRS memory ~ 3 ~ 9 ~3-470 address signals have ~ettled, the control circuit 51 asserts the ROM RAS random access memory row address strobe signal to enable the identified row o~ storage locations in the random access memory 20 to be refreshed. The control circuit 51 then negates the ROM RAS random access memory row address strobe signal to terminate the refresh operation and asserts a REF INCR refresh increment signal which enables the refresh address counter 53 to increment. This process i5 repeated a selected number of times to allow multiple rows in random access memory 20 to be refreshed.

During this time, the HOLD signal remains asserted.
While the HOLD signal is asserted, inverter 67 disables AND
gate 66 so that a change in the condition of the AS address strobe signal does not effect the condition of AND gate 64.
The asserted HOLD signal disables AND gate 70 to isolate the flip-flops 63 and 68 from the SYS CLK system clock signal.
Thus, after the HOLD signal is asserted, the successive ticks of the SYS CLK system clock signal by the processor 10 do not effect the respective conditions of the flip-flops 63 and 68. At the end cf the refresh operations, the control circuit 51 asserts a VID RST video reset signal which causes video timer 52 and flip flops 63 and 68 to reset.

$ ~ ~

As described above, the processor 10, dlsk device~ 23 or network interface 24 may attempt to initia~e a transfer while a video shit register update operation or refresh operation is in progress, and, as part of that transfer, the AS addre6s strobe signal is asserted. In response to the assertion of the AS address strobe signal, the control circuit 51 ensures that the ~DY ready signal is at a negated level. In addition, the control circuit 51 asserts the ADR5 LTH address latch signal which enables the address buf~er 50 to latch the address signals on the data/address lines 15.

Furthermore, the control circuit 51 asserts an ~N PH
CT~ enable phase counter signal which iE coupled to a phase counter 72. The asserted EN PH CTR enable phase counter signal enables the phase counter 72 to load and thereafter increment in response to the successive SYS CLK system clock signals from processor 10. The control circuit 51 uses the phase counter 72 to synchronize restarting of the transfer operation following termina~ion of the video shift register update operation and refresh operations, so as to ensure that the memory operation initiated by, for example, the processor 10, is restarted in synchronism with the same ~ , ~c~ B3-~70 ~42-clock phase of processor 10 during which the processor 10 began the transfer operation.

That iB, if processor 10 initiates a transfer operation in synchronism wi~h phase 2 of a four phase clock, the control circuit restarts the transfer operation, after the video shift register update operation and refresh operations, in synchronism with phase 2. The control circui~ 51 does not, however, receive a signal corresponding to the processor~s clock phases, and so it uses phase counter 72 to count clock phases in response to the SYS CLK
system clock signal, which is ticked to identify the ticks of the processor~s successive clock phases. When the phase counter 72 counts out, it asserts a PHASE CTR TO phase counter time out signal which is coupled to control circuit 51. If the control circuit has not performed all of the successive refresh operations, it again asserts the ~N PH
CTR enable phase counter signal to enable the phase counter 72 to reload. On the other hand, if the control circuit 51 has enabled the last refresh operation, when the phase counter asserts the PHASE CTR TO phase counter time out signal, the control circuit 51 then initiates the transfer operation previously enabled by the processor 10, disk ~31~ 83-470 -~3-devices 23 or network interface 24, using the address latched in the address ~uffer 50, as described above.

The system depicted in the Figs. ensures th~t the video data will be ~ransferred from the video memory 22 to the video shift register 25 expeditiously on the timing out of the video timer 62, even though other units in the system may wish to access one or more of the memories, including the video memory 22. The master control circuit ensures that thic transfer can take place, even while other units may wish to perform a transfer to or from the memory. The processor 10, on the other hand performs arbitration, allowing only one unit to attempt to access a memory at a time to perform a direct memory access operation.

In addition, the system simplifies interrupt processing. In particular, the system enables a number of interrupt request signals to be accumulated and coupled to the processor as a single interrupt request signal. In addition, if a number of units are requesting interrupts, the master control circuit may select one of them according to some order of priority. Further, the system facilitates simplification of the various units which can be connected into it, as the units do not have to have the interface -4~-clrcul~ry to r~6pond to th~ int~r~upt acknowledge operations or transfer their interrupt vectors. ~lnally, the 6y~t8m simpllfies chang;ng the ~nterrupt vectorg, ~ince they ~re all located in a 6ingle un~t~ namely, the re~d only m~mory 21.

The foregoing description has been limited to a ~pecific embodiment of this invention. It will be apparent, however, that variation6 and modificatlons may be m~de to the lnvention, with the a~tainment of ~ome or all oS the advantage~ o the inventlon. Therefore, it 16 the ob~ec~ of the appended claims to cover all such variations and modifications as come within the true spirit and 6cvpe of the invention.

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Claims (5)

1. A digital computer system including a system bus and a plurality of devices connected to the bus, said system comprising:
A. a processor for performing data transfer and inter-rupt servicing operations specified in interrupt service routines, said processor including interrupt acknowledging means for generating an interrupt acknowledge signal in response to an interrupt request signal;
B. memory means for storing data and interrupt service routines;
C. interrupt generating means in each device for genera-ting interrupts when the device requires processor attention; and D. control circuit means for:
i. accumulating the interrupts generated by said interrupt generating means, ii. prioritizing the accumulated interrupts, and iii. signalling a single interrupt request to said processor;
said processor sending an interrupt acknowledge signal to said control circuit means to acknowledge the interrupt request and said control circuit means, in response to the interrupt acknow-ledge signal, directing said processor to the location in the memory means which contains the interrupt service routine associa-ted with the then highest priority accumulated interrupt.

2. The digital computer system of claim 1, wherein said system includes:
A. a video monitor for displaying to a user a video display, and B. video means responsive to said control circuit means for storing video display information associated with said video monitor, said control circuit means controlling the operation of said video means and directing it to perform video update operations to up-date said video monitor display, said control circuit means suspending data transfer and interrupt requests while a video updating operation is performed.

3. The digital computer system of claim 2, wherein said control circuit means controls memory refresh operations of said memory means, said control circuit means suspending data transfer and interrupt requests while a memory refresh operation is performed.

4. The digital computer system of claim 3, wherein said control circuit means re-enables the data transfer operations and interrupt requests after the completion of video update and memory refresh operations, said control circuit means re-enabling the data transfer operations and interrupt requests at a time which does not disrupt a data transfer operation by said processor.

5. The digital computer system of claim 4, wherein said processor includes a system clock which generates timing signals for the operations of said processor, said control circuit means re-enabling data transfer operations and interrupt requests in phase with said system clock.