JPS54139433A - Decision system for end of writing - Google Patents

Decision system for end of writing

Info

Publication number
JPS54139433A
JPS54139433A JP4657778A JP4657778A JPS54139433A JP S54139433 A JPS54139433 A JP S54139433A JP 4657778 A JP4657778 A JP 4657778A JP 4657778 A JP4657778 A JP 4657778A JP S54139433 A JPS54139433 A JP S54139433A
Authority
JP
Japan
Prior art keywords
writing
display
period
cpu1
crt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4657778A
Other languages
Japanese (ja)
Other versions
JPS6140997B2 (en
Inventor
Yasuyo Ishikawa
Kazuo Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4657778A priority Critical patent/JPS54139433A/en
Publication of JPS54139433A publication Critical patent/JPS54139433A/en
Publication of JPS6140997B2 publication Critical patent/JPS6140997B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To secure an assured writing by making use of the non-display period by using the timing pulse which decides the display and non-display periods of the CRT to confirm the writing which is carried out during the non-display period.
CONSTITUTION: The information to be displayed on the CRT screen is written into refresh memory 5 from the input source such as CPU1 and others. To perform this writing during the non-display period, CPU1 performs the address designation for reading circuit 11 and then reads out display timing pulse DISPTMG to decide whether the writing period or not. In case the writing is possible the address data is sent out for memory 5 to carry out writing. After this, the reading and writing actions are confirmed for DISPTMG to complete the writing acation. Thus, the display timing is secured at the time when the data is sent to memory 5 from CPU1, and the disagreement of the data is prevented caused by the automatic stop of the writing action. During the non-display period, the blanking period of the horizontal and vertical timing pulses of the CRT display unit is utilized.
COPYRIGHT: (C)1979,JPO&Japio
JP4657778A 1978-04-21 1978-04-21 Decision system for end of writing Granted JPS54139433A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4657778A JPS54139433A (en) 1978-04-21 1978-04-21 Decision system for end of writing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4657778A JPS54139433A (en) 1978-04-21 1978-04-21 Decision system for end of writing

Publications (2)

Publication Number Publication Date
JPS54139433A true JPS54139433A (en) 1979-10-29
JPS6140997B2 JPS6140997B2 (en) 1986-09-12

Family

ID=12751147

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4657778A Granted JPS54139433A (en) 1978-04-21 1978-04-21 Decision system for end of writing

Country Status (1)

Country Link
JP (1) JPS54139433A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60173580A (en) * 1984-02-20 1985-09-06 株式会社アスキ− Display controller

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01137294U (en) * 1988-03-07 1989-09-20

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5023769A (en) * 1973-06-12 1975-03-14

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5023769A (en) * 1973-06-12 1975-03-14

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60173580A (en) * 1984-02-20 1985-09-06 株式会社アスキ− Display controller

Also Published As

Publication number Publication date
JPS6140997B2 (en) 1986-09-12

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