JPS54139431A - Crt display unit - Google Patents

Crt display unit

Info

Publication number
JPS54139431A
JPS54139431A JP4657578A JP4657578A JPS54139431A JP S54139431 A JPS54139431 A JP S54139431A JP 4657578 A JP4657578 A JP 4657578A JP 4657578 A JP4657578 A JP 4657578A JP S54139431 A JPS54139431 A JP S54139431A
Authority
JP
Japan
Prior art keywords
timing
memory
access
time
vertical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4657578A
Other languages
Japanese (ja)
Inventor
Yasuyo Ishikawa
Kazuo Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4657578A priority Critical patent/JPS54139431A/en
Publication of JPS54139431A publication Critical patent/JPS54139431A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To extend the access time band given from CPU by using only the vertical display timing period among the horizontal and vertical display timing pulses as the writable time band to the refresh memory.
CONSTITUTION: The information to be displayed is writtern into refresh memory 5 through the input source such as CPU1 or the like. The information of memory 5 is converted into the pattern signals via pattern generation circuit 6 and then displayed on CRT via P/S circuit 7 and others. At the same time, timing pulse generation circuit 11 forms the access timing signal to be supplied to memory 5 from the input source. In the display unit of such constitution, the border part of 10% is provided at the up and down plus right and left areas each of display screen 13 of CRT to secure effective display screen 14. Here, the blanking timing composed of the flyback line erasing timing and the border timing to form screen 14 is used to be allotted to the access timing given from the CPU and other. In this case, only the vertical blanking time is uded since the horizontal blanking time is extremely short.
COPYRIGHT: (C)1979,JPO&Japio
JP4657578A 1978-04-21 1978-04-21 Crt display unit Pending JPS54139431A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4657578A JPS54139431A (en) 1978-04-21 1978-04-21 Crt display unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4657578A JPS54139431A (en) 1978-04-21 1978-04-21 Crt display unit

Publications (1)

Publication Number Publication Date
JPS54139431A true JPS54139431A (en) 1979-10-29

Family

ID=12751094

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4657578A Pending JPS54139431A (en) 1978-04-21 1978-04-21 Crt display unit

Country Status (1)

Country Link
JP (1) JPS54139431A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5937588A (en) * 1982-08-25 1984-03-01 シャープ株式会社 Crt display controller
JPS59116783A (en) * 1982-12-24 1984-07-05 株式会社東芝 Display memory access system
JPS60173580A (en) * 1984-02-20 1985-09-06 株式会社アスキ− Display controller

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5023769A (en) * 1973-06-12 1975-03-14
JPS5082939A (en) * 1973-11-24 1975-07-04

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5023769A (en) * 1973-06-12 1975-03-14
JPS5082939A (en) * 1973-11-24 1975-07-04

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5937588A (en) * 1982-08-25 1984-03-01 シャープ株式会社 Crt display controller
JPH0120429B2 (en) * 1982-08-25 1989-04-17 Sharp Kk
JPS59116783A (en) * 1982-12-24 1984-07-05 株式会社東芝 Display memory access system
JPH0548474B2 (en) * 1982-12-24 1993-07-21 Tokyo Shibaura Electric Co
JPS60173580A (en) * 1984-02-20 1985-09-06 株式会社アスキ− Display controller

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