JPS59116783A - Display memory access system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an access method for a display memory that stores display data of a CRT display gray device, which constitutes one terminal of an information processing apparatus.

Technical Background of the Invention and its Problems] CRT display devices are widely used as output devices in microcomputer systems. At this time, the interface between the microcomputer and the CRT display device includes a CRT display control circuit (hereinafter referred to as CRT display control circuit).
RT controller) is provided. Recently, C
Among RT display devices, CRT display devices with high display scanning frequencies have appeared, and it has become difficult for both the CPU and the CRT controller to access display data during one character display period, as was the case in the past. CRT controllers can be divided into aperiodic type and periodic type by the data access method with the microcomputer.In the aperiodic type,
Although data can be accessed with the microcomputer at any time, it has the disadvantage that screen flickering is noticeable. Also, data is accessed between the microcomputer and the microcomputer using periodic mononoke and vertical blanking periods, so there is no flickering on the screen, but the display data transfer period is limited to the vertical blanking period. Moreover, in order to know the vertical blanking period, many functional circuits including a count circuit etc. are required, and therefore the amount of hardware increases significantly. Conventionally, when a synchronous method was adopted to eliminate screen flickering, problems occurred in terms of hardware configuration, display data transfer amount, etc., and in order to solve these problems, an aperiodic method was adopted. There was a problem with flickering on the screen.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a display memory access method that does not cause screen flickering and can improve display data transfer efficiency with a simple hardware configuration.

[Summary of the invention]

The present invention enables a CPU to take in a display timing signal obtained from a display control circuit as status information indicating a display period/non-display period at any timing, and determines the state of the status information based on the status information. ,
The system determines the horizontal and vertical blanking periods, accesses the display memory during each blanking period, and transfers the display data.This reduces the amount of hardware required and eliminates screen flickering. This can improve the display data transfer efficiency.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram showing one embodiment of the present invention. In the figure,
100 is a microprogram processing unit (hereinafter referred to as CPU) that controls the entire system; 101 is a CPU;
The main storage device (hereinafter referred to as M-
(referred to as RAM). Reference numeral 102 denotes a display memory (hereinafter referred to as DSP-RAM) that stores display data sent from the CPU 100 and is read out and controlled by a display control circuit to be described later in conjunction with display operations. 103 is the above DSP
- Has address generation function of RkM102, vertical synchronization signal (■), horizontal synchronization signal ■2 display timing signal (DS
This is a display control circuit (hereinafter referred to as a CRT controller) that generates PTMG) and the like.

104 is I1 designated by the CPU 100 as a specific port.
When executing the 0 input command, the CRT controller 103
This is a display status output circuit (STUM) that outputs a display timing signal (DSPTMG) generated from the STUM as status information indicating a display period/non-display period. 10
5 is an address bus (A-BUS), and J06 is a data bus (D-BUS). 107 is a display timing signal (DSP
TMG) to the display status output circuit 104. 108 is a CRT controller 103
This is a CRT display unit that displays and outputs the turn of characters, figures, etc. according to the video signal (VD) under the control of the video signal (VD).

The CPU 100 reads status information (DS PTMO) from the display status output circuit 104 when controlling access to the DSP-RAMJ 02. If the read status information indicates the display period, repeat reading the above status information (execution of I10 manual command specifying a specific port), and when the status information changes to the non-display period, It is determined that it is a horizontal blanking period, and the DSP-RAMIO,? access. Also, if the read status indicates a non-display period, the status information is read again after one horizontal blanking period, and if the read status information indicates a non-display period, the vertical blanking period Judging that,
Access to the DSP-RAM 102 is executed within that period. FIG. 2 is a flowchart showing the access control procedure of the DSP-RAMJ 02 by the microprogram processing of the CPU J o at this time, and FIG. 3 is an operation explanatory diagram for explaining the operation.

The operation of one embodiment will now be described with reference to FIGS. 1 to 3. CPU 1001dM - Executes processing according to the program stored in RkMlol, and also
The controller 103 receives vertical and horizontal synchronization signals (V, H
), a display timing signal (DSPTMG), etc., and at a timing synchronized with these signals, display data is read out sequentially from the DIP-RkM 102, and a pattern according to the data is displayed on the CRT display section 10.
8 is displayed and output. At this time, CRT controller 1
Display timing signal (DSPTMG) generated from 03
) is the display status output circuit 10 via the signal line 107.
4 is given. Here, the CPU 100 uses DIP-
When an access request for RkM102 occurs, a specific port is designated and the I10 manual command is executed, and the display status output circuit 104 outputs a display timing signal (DSPTMG).
is read as status information indicating the display period/non-display period. Then, depending on the state of the read status information, a series of operations according to the flow shown in FIG. 2 is executed. That is, the display timing signal (DSPTMG) is read from the display status output circuit 104 as status information indicating a display period/non-display period, and it is determined whether the status information indicates a display period or a non-display period. (Figure 2 steps a and b). Here, if the display period is indicated (for example, TP in Figure 3, when the read operation of the input status information is repeatedly executed and the state changes from the display period to the non-display period (for example, TP in Figure 3))
Then, the DSP-RAM 102 is accessed in predetermined time units within one horizontal blanking period (steps c, d, and e in FIG. 2). In addition, when determining the display period/non-display period of the status information (Step b in Figure 2), if the non-display period is indicated, the status is not read in any period of the blanking period. Since it cannot be determined whether the
TP, ~TP,) and read the status information again (steps g, h in FIG. 2). Here, if the status information indicates a non-display period (TP, ~TP, in FIG. 3), it is determined that the vertical blanking period has entered, and the DSP-RAM 102
(Steps i and j in Fig. 2), at this time, the vertical blanking period is exceeded and the DSP-RkM is accessed.
Although there is a possibility that l02 is accessed, the probability of that happening and the overtime are extremely small, so the screen flickers are very inconspicuous, and there is no problem in practical use.

Furthermore, if the status information after waiting one horizontal period indicates a display period (for example, TP, ~TP, in FIG. 3), it is determined that the blanking period was horizontal blanking. , the status information reading operation is repeated until the non-display state is indicated (steps i, c, . . . in FIG. 2).

In this way, the access control of 8P-RAMZ OX is as follows.
This is repeatedly executed during the memory access request period of the DIP-RkM 102. Therefore, the DSP-
Access to the R input M102 is efficiently performed using horizontal and vertical blanking periods. Moreover, it can be realized with very little hardware, and there is almost no screen flickering.

〔Effect of the invention〕

As detailed above, according to the present invention, in the display memory access method, the CPU takes in the display timing signal obtained from the display control circuit at an arbitrary timing as status information indicating the display period/non-display period. The horizontal and vertical 'f'57 king periods are determined from the state of the status information, the display memory is accessed during each blanking period, and the display data is transferred. with less hardware and without causing screen flickering.
Display data transfer efficiency can be increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a flowchart showing a display memory access control procedure in the above embodiment, and FIG. 3 is an explanatory diagram of the operation of the above embodiment. 100... Microgram processing unit (CPU). 101... Main memory device (M-RAM), 102...
Display memory (DSP-RAM), 103... Display control circuit (CRT controller), 104... Display status output circuit (8TUM), 105... Address bus (A-BUD), 106... Data Bus (D-B
US), Z o y...Signal line, 10B...CRT
Display section, D8PTMG...Display timing signal. Figure 1 Part 2

Claims (2)

[Claims] (1) A display memory that stores display data sent from the CPU, horizontal and vertical synchronization signals, and a display timing signal, and outputs the display data from the display memory in synchronization with the display timing signal. A display control circuit for reading out. and a status output circuit that outputs status information based on the display timing signal to the CPU as status information indicating a display period/non-display period upon input of a read signal from the CPU, An access method for a display memory, characterized in that when accessing the memory, a status information read signal is sent to the status output circuit, and the read status information is also accessed to the display memory. (2) When the read status information indicates a display period, the CPU repeats reading the status information, and determines that it is a horizontal erasing period when the read status information changes to a non-display period. If the read status information indicates a non-display period, the status information is read after at least a horizontal erasing period, and the read status information is read out. 2. The display memory access method according to claim 1, wherein when the information indicates a non-display period, it is determined that it is a vertical erasing period and the display memory is accessed.