JPS6029837A - Information processor - Google Patents

Abstract

PURPOSE:To set a video memory for display in a main storage memory and to facilitate its handling by providing a specifying means which specifies an area in the main storage memory and an address deciding means for access to the main storage memory. CONSTITUTION:The specifying means for specifying the area in the main storage memory and the address specifying means which decides on whether access to the main storage memory is addressed to said area in the main storage area or not are provided. For example, a readout address in the main storage memory 4 is specified and reported to a CRT controller 15 under the control of a CPU1, and the CRT controller 15 outputs a horizontal and a vertical synchronizing signal and a video signal to a CRT display device 16. Then, when an image is displayed on the screen, an automatically updated address output is accessed in the main storage memory 4 through an I/O bus 14 and an address bus 3. Then, image data read out of the main storage memory 4 is inputted to the CRT controller 15 through a data bus 2 and an I/O bus 14.

Description

Description: TECHNICAL FIELD The present invention relates to an information processing device, and more particularly to an information processing device that allows a portion of a main memory to be used recursively, thereby allowing it to be shared as an image memory.

BACKGROUND OF THE INVENTION Recently, the number of small and portable microcomputer devices has increased. When a CRT is used as a display section of such a computer device, there are many disadvantages in terms of portability, such as the large size of the CRT and the need for a high-voltage power source. However, nothing beats CRT in terms of the amount of information that can be displayed on one screen and the price. Therefore, a type of portable microcomputer device is being considered, for example, that uses a small liquid crystal display with low power consumption when used on the move, and then connects to a CRT when returning to the office to process data. There is. The capacity of the image memory used in this type of microcomputer device differs greatly depending on whether it is a liquid crystal display or a CRT device, but conventionally, when the CRT device is not in use, image memory that is not needed is always kept in the main body. When connecting to a CRT device with a dedicated image memory, a complicated circuit is used to transfer the image data from the main memory to the CRT device.
It was moved to the equipment side.

Generally, when displaying characters or graphics, the pixels of the display device and the bits of the image memory are in one-to-one correspondence, and the dot patterns of the characters or graphics are drawn by turning on the bits of the image memory. Also, characters and figures are displayed on the screen, for example, characters are displayed on the bottom line of the screen, and when the user wants to see the next line, a control called scrolling is performed. This is achieved by controlling the readout start address of the image memory to be shifted relative to the display price. Therefore, in an apparatus having a dedicated image memory for one screen, the scrolling process can be easily performed because the readout address of the image memory returns to address 0 when it exceeds the maximum memory address. However, if you try to use a part of the main memory as image memory, the readout address returns to address O from the maximum, and the image memory occupies a discontinuous area in the main memory, making it difficult to handle it. She is a troubled woman.

Purpose The present invention has been made in view of the disadvantages of the above-mentioned prior art, and its object is to provide an information processing device in which display image memory can be set in the main memory and the handling thereof is easy. Our goal is to provide the following.

EXAMPLE Hereinafter, an example of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a portable computer according to an embodiment of the present invention.

In the figure, 1 is the central processing unit (CPU) that controls the main control of the portable computer, 2 is the memory data bus, 3 is the memory address bus, and 4 is the RA
M is a main memory consisting of ROM. The main memory 4 of the embodiment is composed of a maximum of four memory blocks of 4 bytes, and each memory block is selectively selected by chip select signals C3O to C33 output from the decoder 5. Incidentally, the signal C8O selects the ROM block containing the program, and the signal C3l
-C33 selects a RAM block in the work area.

However, in the configuration of the embodiment, R to be selected by signal C$3
It is assumed that the AM block 43 is not mounted.

Next, latches 6.7 each consist of 2 bits, and information corresponding to the most significant 2 bits of address/hence 3 is set and held. Information is set to the latch 6.7 using the upper two bits of the data bus 2, and when CPtJl executes a dedicated set command, a set signal is sent via the respective signal lines 8.9.

10 is a comparator that compares the output of latch 6 and the content of the most significant 2 bits of address/< signal 3, and when the content of input terminal B is greater than the content of input terminal A, the signal A< B
Output. 11 is a subtracter which subtracts the content of input terminal B from the content of input terminal A and outputs an output A-B.

The output A-B of the subtracter 11 is input to the input terminal B of another subtracter 13 via a gate circuit 12 consisting of an AND gate. Further, the contents of the most significant two bits of the address/hess 3 are input to the other input terminal A of the subtracter 13, and here again, the contents of the input terminal A are changed from the contents of the input terminal B.
The content of is subtracted, and the output A-B is input to the decoder 5.

14 is an I10 bus of the CPU 1, and the main part of the path consists of a data bus 2 and an address bus 3.

Various controllers are connected to the I10 lotus. 1
5 is a CRT controller, and external independent CR1
A display device 16 can be connected. Example CR1
The display device 16 does not have a dedicated image memory therein, but instead directly utilizes the image memory function provided in the main memory 4. This point will be discussed later.

17 is an LCD controller, which is permanently installed on the main body.
Controls the CD display 18. A keyboard controller 19 controls a keyboard 20 which is also permanently installed in the main body. Although not shown, a controller for controlling an external mini-disc device can be added if necessary.

In the above configuration, the manner in which images are displayed on the CR1 display device 16 will be explained in detail below.

FIGS. 2A and 2B are explanatory diagrams showing the correspondence between the image memory and the display screen. First, FIG. 2(A) shows one mode of scroll display. In the figure, 4 indicates the entire area of the main memory, of which addresses a to C are set for image memory. In the embodiment, the area of the image memory is set as a multiple of the memory block (4 KB). Furthermore, no memory block is mounted from address C to address d.

Here, a pattern image that has already been scroll-written from address a to address C in the memory is shown. Furthermore, when scrolling and displaying this on the screen, for example, the image data from address b to address C in the memory is read out and displayed on the upper part of the screen 21, and then the image data from address a to address b in the memory is read out in order. If the image data is read out and displayed on the lower side of the screen 21, the original triangular pattern image will be displayed on the screen 21.

In FIG. 2(B), this is the reverse, and the original triangular pattern image is written at addresses A to C in the memory.

In order to scroll and display this, the image data from memory address B to address C is read out sequentially and displayed on the screen 21.
Then, when the image data from address a to address b in the memory is read out and displayed on the lower side of the screen 21, a scrolled triangular pattern image is displayed on the screen 21. It is. In this way, the scroll display can be done by shifting the memory read start address as the display screen is scanned. Originally, such a scroll display would only provide the memory read start address, and the rest of the control would be done. It is preferable that this is done automatically for one screen. If a dedicated image memory is provided as in the past, there is generally a pairwise correspondence between the dedicated image memory and the display screen, and accesses exceeding the maximum memory address are automatically converted to accesses from address 0. Easy to control. However, since the computer of this embodiment intends to share a portion of the main memory for this purpose, the memory peripheral configuration as shown in FIG. 1 was provided.

The operation will be explained below with reference to FIG. The CRT controller 15 outputs horizontal and vertical synchronization signals and video signals to the CRT display device 16. Also CRT controller 1
5 has a functional configuration corresponding to DMA, and an address output that is automatically updated during display accesses the main memory 4 via the I10 bus 14 and the address bus 3. The image data read from the main memory 4 is transferred to the CRT controller 1 via the data bus 2 and the I10 bus 14.
5 is input. Such a read cycle is repeated for one screen of CRT display.

The control performed by the CPU on the CRT controller 15 before the start of display is to set the read start address in the main memory. When this value is set in the CRT controller 15, the readout phase of the main memory with respect to the vertical synchronizing signal of the CRT is determined, and display control is thereafter performed using this readout phase until a new setting is made. Further, the CPUI performs the following preprocessing in order to cause the specified image memory area on the main memory 4 to operate as if it were an image-only memory. One is for latch 6 and sets the maximum memory block address (eg 2) used as image memory.

The other is for latch 7 and is the starting memory block address -1 (for example 0) used as image memory.
Set. From now on, it is sufficient to simply send a display start command to the CRT controller 15.

Here, the subsequent operation will be explained with reference to FIG. 2(B) again. It is assumed that the CPUI has set the read start address of the main memory to the CRT controller 15. Therefore, reading from the main memory 4 is performed sequentially from address b toward address C. During this period, the comparison of the comparator 10 is not satisfied and its outputs A and B are O, so the output of the gate circuit 2 is deenergized. That is, the content of the input terminal B of the subtracter 13 is 0, and the content of the two most significant bits of the address bus 3 is passed through the input terminal A of the subtracter 13 without being subtracted and is given to the decoder 5 as is. The selection signal output from the decoder 5 during this period is assumed to be cs2. In other words, addressing within the area designated as image memory is no different from normal addressing. Eventually, the main memory memory will be read from C.
Once the address is reached, the addresses after that correspond to unspecified memory blocks, and moreover, no memory is implemented.

In other words, the output of the decoder 5 attempts to output the selection signal C33. At this time, the outputs A and B of the comparator 1o are satisfied and the gate circuit 12 is energized. The content of the output A-B (2-0) of the subtracter 11 is 2, which is applied to the input terminal B of the subtracter 13. Since the content of input terminal A is 3, the content of its output A-B (3-2) is l. Therefore, the selection output signal of the decoder 5, which should be C33, actually becomes C3I, and the memory address corresponding to address a is substantially read out. In other words, once the read address from the CRT controller 15 is given the scroll read start address,
Thereafter, the number is sequentially increased from the bi address to the C address, and further from the C address to the d address. A latch 6 stores the upper limit block address of the image memory, and a comparator 1O determines whether the actual access address on the rear address path 3 exceeds this range.
is being monitored. If the number of memory blocks is exceeded, the gate circuit 12 is activated by the output of the determination, and the actual access address is pulled back by the number of memory blocks specified in the image memory.

For this reason, the CRT controller 15 does not require any special control, and the main memory can be used as if it were a dedicated image memory.

Although the scroll read control has been described above, the scroll write control to the main memory 4 is performed in the same manner. In other words, the triangular scroll pattern in the main memory 4 shown in FIG. 2(A) can be easily obtained by scroll writing from the CPUI. The address bus 3 is shared by the CPU and the I10 bus in a time-sharing manner, so even when the CPU executes its own instructions, the memory in the designated area can be used as if it were a dedicated image memory. be. Therefore, the CPU only has to execute the process of writing the triangular pattern images all at once from the address b of the main memory 4 toward the address d. In other words, the process that requires determination for scroll writing is only changing the address b, and the process of writing graphics does not require any changes. If the scroll writing turn written in this way is read out again by the scroll, then the t52 diagram (A
) can be obtained as described above. In this way, graphics processing on the main memory, which conventionally requires complex address processing, can be performed extremely easily.

When using an LCD display, less image memory is required and the settings can be changed to, for example, 1 memory block (4
KB) can be controlled in exactly the same way. Therefore, the main memory is used efficiently according to its purpose. Further, the image memory can be specified as an arbitrary multiple of the memory block. In the embodiment, it is possible to set the number to be a multiple of 4KB, or it is also possible to configure the memory block into IKB and set it to a multiple of IKB. In this way, it is easy to subdivide as necessary. Additionally, you are free to not implement unnecessary memory blocks depending on your purpose.
This does not cause any problem in address control. One problem with the configuration of the embodiment is that when the main memory 4 is fully installed, an access that satisfies the output A<B of the comparator 10 does not occur in the access to the last memory block 43. However, since the functions of latches 6 and 7 essentially point to the beginning and end of designation as image memory, image memory can be designated to any memory block located in the middle of the main memory. However, the above-mentioned operation can be obtained anywhere.

Incidentally, in the above-mentioned embodiment, a practical configuration example has been described, but it is obvious that various modifications can be made without departing from the idea of the present invention. For example, a configuration that allows specifying memory addresses instead of specifying memory blocks,
A configuration in which a difference value is given directly in place of the latch 7 and subtractor 11 configuration, a configuration in which the upper limit address of the specified area corresponds to the upper limit address of the mounted memory and the comparator 10 is omitted, and the access to the main memory memory is large. A configuration that performs the same function when directed to a small address, a configuration that uses an address conversion means that uses a ROM etc. to generate a special O address, and energizes the address conversion means with the output of the comparator 10 etc. etc.

Effects As described above, according to the present invention, a part of the main memory can be designated as an image memory, and that area can be used as if it were a dedicated image memory. Therefore, there is no need to be aware of address discontinuity in the image memory when writing scroll figures to the main memory or scrolling figures on the display screen using software, and the burden on the software is extremely reduced. . Furthermore, since any location and size of the main memory can be defined as image memory, it is possible to easily handle the amount of display information required by the display device.
It is possible to have a flexible system configuration while making effective use of memory. ′

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a portable computer according to an embodiment of the present invention, and FIGS. 2(A) and CB) are explanatory diagrams showing the correspondence between an image memory and a display screen. Here, 1... central processing unit
(CPtJ), 2...Thetanox, 3...Address/<su, 4...Main memory, 5...Decoder,
6.7...Latch, 8.9...Signal line, 10...
Comparator, 11° 13... Subtractor, 12... Gate circuit, 14... I10 bus, 15... CRT controller, 16... CRT display device, 17... LCD controller, 18... ...LCD display amount, 19...Keyboard controller, 20...Keyboard. 91'52 - (A) - d,, L - - J Figure 2 (B) 6 - - J

Claims (1)

[Scope of Claims] ('l) Specifying means for specifying an area in main memory, and determining whether access to the main memory is outside the area specified by the specifying means. An information processing apparatus comprising an address determining means and an address converting means for converting an access to the main memory into an address within the specified area based on the output of the address determining means. (2) The information processing device according to claim 1, wherein a part of the main memory is shared as an image memory. (3) The information processing device according to claim 1, wherein access to the main memory is performed even to an address where the memory is not installed.