JP3454113B2 - Graphics display - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a graphic display device, and more particularly to a graphic display device in which a plurality of information are integrated in the same memory in order to enable a graphic moving image display in a small and low cost system.

[0002]

2. Description of the Related Art As an example of a processor for processing high-speed three-dimensional graphics, "3D CG drawing LSI, PC realizes 300,000 polygons / second: Nikkei Electronics, July 17, 1995 (No. 640), pp109-
120 "has been introduced. This processor is provided with three types of memory dedicated to the processor: a memory for texture, a memory for frame buffer, and a memory for local. This architecture is advantageous for improving performance. Therefore, it is not suitable for small-sized, low-priced devices such as portable devices for individuals because it requires multiple types.
As an example of a graphics system in which graphics information is unified in the main memory of PU and the number of memories is reduced,
There is JP-A-5-257793. This is a system in which a CPU program, texture data, frame buffer, etc. are integrated in one type of memory.

[0003]

According to the above-mentioned prior art, it is premised that the memory access capability is sufficiently high such as several hundred MB / s. Therefore, in the above prior art, a sufficient time for reading the display data is secured. In order to have a high-speed memory system, the data bus width for memory access must be widened or a high-speed memory must be provided, which hinders downsizing and cost reduction of the system.

Therefore, if the memory access capability is lowered,
In order to secure the display data read time, it is necessary to control the display data read timing by memory access other than display. In particular, since the access from the CPU is frequent, it affects the reading of display data.
In the above-mentioned prior art, there is no description about control of read timing of display data by memory access other than display.

Therefore, an object of the present invention is to allow the graphics processor to control display data read timing by memory access other than display.
It is an object of the present invention to provide a graphics display system and method capable of reducing the buffer size required for buffering display area data.

[0006]

In order to achieve the above object, according to the present invention, a CPU for generating drawing procedure information composed of types of graphics figures to be displayed, vertex parameters, etc., and drawing procedure information and bits. A memory that stores map information, a display that displays drawing data in the memory, a drawing that is sequentially drawn in the memory based on drawing procedure information, and a memory display to display bitmap information on the display. The memory is a graphics display device that has a graphics processor for reading and the memory is accessed by both the CPU and the graphics processor, and the graphics processor continuously transfers to the memory. The graphic processor is equipped with address detection means to detect whether When transferring, characterized in that varying the number of transfer of data to the memory by an address discontinuity information detected by the discontinuous address detecting means.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an example of the system configuration of a graphic processing device using a graphics processor according to the present invention. The CPU 10 controls the entire apparatus and executes a program for displaying a graphic on the display 51. The CPU 10 has a cache 101 built therein. The main memory 11 is a memory that stores data and programs processed by the CPU 10. The CD-ROM controller 12 is a controller for accessing a CD-ROM that stores graphic information.
Reference numeral 3 is a controller for transmitting / receiving information to / from another device (not shown). Graphics processor 20
Is a processor for drawing a graphic in the display area in the graphics memory 40, reading the drawn data, and displaying the graphic on the display 51. DAC (Digi
The tal to analog converter 50 converts the display data in digital format output by the graphics processor 20 into analog data.

It is desirable to use DRAM (Dynamic RAM) as an element constituting the graphics memory 40. This is because DRAM is
This is because the degree of integration of transistors with respect to the chip area is high. Accessing a DRAM with discontinuous addresses takes a long time. However, the DRAM has an access method called high-speed page mode access, and has a feature that high-speed access can be performed in continuous access when the upper part of the address (for example, bit 9 or more) matches.

The graphic displayed by the graphic processing apparatus is intended to display a graphics moving image. That is, 1
By gradually changing the size and position of the graphic every 60 seconds or 1/30 second and continuously watching the screen, a moving picture of the graphics graphic is displayed. Therefore, CPU1
0 or the graphics processor 20 is 1/60 second or 1
It is necessary to draw one screen every 30 seconds.
In order to draw a graphic for one screen, the procedure is as follows.

(1) Coordinate conversion of graphic data by the CPU 10 The direction, size, etc. of the graphic to be displayed are calculated, and the vertex coordinates of the graphic are calculated. Generally, a complicated figure is configured by combining many simple figures such as a triangle and a quadrangle. Therefore, the coordinates of all the vertices of these figures are calculated.

(2) Creation of a display list by the CPU 10 In order to draw the above-mentioned many simple figures in the graphics memory 40 by using the graphics processor 20,
It is converted into a command format that can be executed by the graphics processor 20 and transferred to the graphics memory 40.
Normally, the commands are connected by the number of the simple figures. A combination of these commands is called a display list. The display list has a size of several tens to several hundreds of Kbytes.

(3) Drawing by the graphics processor 20 The graphics list is sequentially read by the graphics processor 20 and drawn in the drawing area in the graphics memory 40 according to the command shown in the list.

(4) Display by Graphics Processor 20 The drawn graphic is the graphics processor 2
0 is read at a timing matched with the display 51 and displayed on the display 51.

From (1) to (4) above, 1/60 seconds or 1
/ Repeat every 30 seconds.

Next, an outline of the inside of the graphics processor 20 will be described. CPU I / F21 is CP
U10 performs control for accessing registers such as the system control register 32 and the graphics memory 40. The drawing unit 23 fetches the display list in the graphics memory 40 and draws according to the command shown in the list. Parameter converter 2
2 converts the parameters of the command as needed. The display controller 24 is a control unit for displaying the data drawn by the drawing unit 23. As described above, since the graphics processor 20 accesses the graphics memory 40 every time it performs some processing,
Increasing the access efficiency of the graphics memory 40 leads to improvement in processing speed. Therefore, the graphics processor 20 uses a cache or F for each access request unit.
Having an IFO improves access efficiency. CPU
The FIFO 25 is a graphics memory 4 of the CPU 10.
Speed up access to 0. Address mismatch detection 251
2 detects whether the addresses of the data to be written in the graphics memory 40 are discontinuous. The cache 1 16 is dedicated to commands, the cache 2 27 is dedicated to textures, and the cache 3 28 is dedicated to drawing. The address mismatch detection 2807 detects whether the addresses of the data to be written in the graphics memory 40 are discontinuous. It also has a display buffer 29 for display data. Memory controller 30
Receives an access request to the graphics memory 40 such as the cache or FIFO, determines the priority order, and controls the access to the memory. The memory controller 30 gives the highest priority to the access request from the display controller 24, but during the access from the CPU 10 and the drawing unit 23, the access request may not be interrupted and the display controller 24 may wait. The system control register 32 is a register that specifies the operation mode of the graphics processor 20. In this register, the MEM (ME) that specifies the width of the upper bits of the address to be compared in the address mismatch detection 2512, 2807.
mory Mode) There is a bit. For example, 4 Mbit DRA
When using M, upper 13 bits, 16 Mbit DRA
When M is used, it is specified to compare the upper 12 bits.

Next, the terminal function of the graphics processor 20 will be described with reference to FIG.

(1) System system This is a terminal for setting system mode, inputting clock and reset. The graphics processor 20 can input independent clocks for the drawing system and the display system.
Therefore, regardless of the type of the display device 51, the drawing system can always perform high-speed processing.

(2) CPU system CPU I / F terminal. The CPU 10 can access the entire space of the graphics memory 40 and internal registers such as the system control register 32. C to access the graphics memory 40
When S0 terminal is set to Low and register is accessed, CS
Set 1 terminal to Low. The write access to the graphics memory 40 has two write enables so that byte access is possible. In addition, there are DREQ and DACK terminals for controlling DMA transfer, WAIT terminal for extending the bus cycle, and IRL terminal for generating an interrupt to the CPU 10.

(3) Terminals for supplying power to the power system include a dedicated PLL terminal for clock control and other general terminals.

(4) Dot clock output (DCL) as a display terminal
K), display data output (DD0-DD15), sync signal input / output terminals (HSYNC, VSYNC), and the like.

(5) A DRAM is used as an I / F with the memory type graphics memory 40.
(Dynamic RandomAccess Memory) has a terminal that can be directly connected.

Next, the drawing command of the graphics processor 20 will be described with reference to FIG.

(1) Rectangle drawing command Draws while transforming the rectangular texture data into an arbitrary quadrangle. If the texture data is binary, color expansion is performed.

(2) LINE Draw a single line or multiple lines.

(3) MOVE Moves the drawing start point.

(4) LOFS This is a command for shifting the origin of drawing coordinates. The command after this command is executed draws with the coordinates shifted by the amount specified by this command with respect to the coordinate parameters shown in the display list.

(5) AFFIN This is a command for designating rotation, enlargement, and reduction when drawing a figure. The coordinates are rotated (or enlarged or reduced) by the amount specified by this command with respect to the coordinate parameters shown in the display list and drawn.

(6) JUMP This is a command for branching the display list.

(7) GOSUB Call the display list subroutine.

(8) RET Return from a subroutine.

(9) TRAP Finish fetching the display list.

(10) Cache 227 which is a cache of FLASH texture data
The data existing therein is invalidated, and the data is newly read from the graphics memory 40.

Next, the register function of the graphics processor 20 will be described with reference to FIG.

(1) The system control register SRES initializes the drawing unit 23 by software, and the DRES initializes the display controller 24 by software. The DAC switches the display area (frame buffer area). The RS starts fetching the display list. The CAM specifies the type of the cache 101 in the CPU 10. CPU when CPU 10 stores data in graphics memory 40
10 is characterized by the cache 10 of the CPU 10.
When 1 uses the copy back method, the data is written collectively by the line size of the cache.
When the write-through method is adopted, data is written in 1-word units.

Here, the difference in the writing time to the graphics memory 40 due to the continuity of addresses will be described.

When data is written from the CPU FIFO 25 to the graphics memory 40, if the addresses of the data to be written are continuous, the graphics memory can be written from the CPU FIFO 25 in a short time as described above in the feature of DRAM. You can write to 40. In this case 1
When 6-word data is written, the data can be written in about 20 cycles. On the other hand, when the addresses of the data to be written are discontinuous, the time for writing from the CPU FIFO 25 to the graphics memory 40 becomes long due to the characteristics of the DRAM as described above. In the worst case, all of the CPU FIFO 25 may be discontinuous. In this case, it may take about four times as long as the continuous addresses (up to 80 cycles). Therefore, when writing data to the graphics memory 40, the writing time can be shortened by always making the addresses continuous, and efficient memory access becomes possible.
This operation will be described later in detail.

(2) The status register VBK notifies the switching of display frames. TRA
Notifies that the TRAP command has been executed and the fetch of the display list has been completed. The DBF indicates which of the two frame buffers is currently being displayed.

(3) Status register / clear register Clears the corresponding status register bit.

(4) Interrupt enable register CPU is controlled by each bit of the corresponding status register.
Specifies that 10 is to be interrupted.

(5) The rendering mode MWX specifies whether the horizontal width of the screen is 512 pixels or less, or 513 pixels or more and 1024 pixels or less. GBM specifies whether one pixel has 8 bits or 16 bits.

The MEM designates the bit width of the address to be compared in the address mismatch detection 2512, 2087 depending on the type of the graphics memory 40.

(6) Display mode The SCM specifies whether the display is interlaced or non-interlaced. The TVM specifies whether it is the TV synchronization mode or the master mode. RC
YN specifies the number of refresh cycles of the graphics memory 40.

(7) Display size Designates the size of the display screen in the X and Y directions.

(8) Display start address The start addresses of the two frame buffers on the graphics memory 40 are designated.

(9) Display list address The start address of the display list on the graphics memory 40 is designated.

(10) Source Area Start Address The start address of the storage area for texture data is designated.

(11) Display control related registers Register numbers 10 to 19 are registers related to display control. The timing of reading the display data is set according to the size of the display screen, the cycle of the horizontal / vertical synchronization signal, and the like. Further, the display reset output register sets the color value to be displayed on the screen when the display reading is not performed. For example, the screen can be blue back (blue display) while the display operation is stopped.

(12) Command status register This register notifies the memory address when fetching the display list is stopped.

Next, a FIFO method for the CPU 10 to access the graphics memory 40 will be described. FIG. 5 is a block diagram of the CPU FIFO 25. CPU1
Every time 0 performs a store operation to the graphics memory 40, a write request signal comes from the CPU I / F section 21. Then, the counter 252 is counted up, and the write address and data of the CPU 10 at that time are stored in the FIFO 250. FIFO 250 is 1
Stores 6 words of data. Eventually the counter 252 becomes F
If it is found that the FIFO is full as compared with the IFO capacity (16 words), the flip-flop 258 is set. As a result, the CPU I / F unit 21 is notified that the FIFO is busy, and the CPU 10 is prevented from storing any more data. On the other hand, the memory controller 30 outputs a write request to the graphics memory 40. The memory controller 30 updates the counter 256 every time one word of data is written.
The IFO counter update signal is output. At this time, the address to be written in the graphics memory 40 is set in the register 251.
1, and the higher-order plural bits of the address to be written next and the address stored in the register 2511 are compared by the mismatch detector 2512. The bit width to be compared at this time is designated by the MEM bit 320 of the system control register 32. If the two addresses do not match (that is, the addresses written to the graphics memory 40 are not continuous), the flip-flop 258 is reset. Flip-flop 2 by discontinuous address
When 58 is reset, in order to write the data still remaining in the FIFO to the graphics memory 40, the flip-flop 258 is set again by the write end signal indicating that the writing of the data before the reset is completed. The counter 256 is constantly compared with the value of the counter 252 by the coincidence detector 255. The counter 256 is a FIFO read counter, and the counter 252 is a FIFO write counter. When the two match (that is, when the number of words written by the CPU 10 is read to the memory controller 30), the flip-flop 258 is reset to stop writing to the graphics memory 40. Further, the free-run counter 254 operates so as to write the data of the FIFO 250 to the graphics memory 40 when there is no writing by the CPU 10 for a certain period. Also, CPU1
When 0 reads the graphics memory 40 or when the drawing unit starts fetching the display list, it operates so as to write the data in the FIFO 250 to the graphics memory 40 prior to them. FIFO
Since 250 holds a maximum of 16 words of data, CP
Data can be written from U10 at a maximum of 16 words at a time.

Next, the drawing cache will be described. FIG. 6 is a block diagram of the cache 3 28.
Although this cache is dedicated to drawing, the drawing unit does not read the data in this cache. That is,
Since it does not have a function of performing data calculation with the rough sketch of the drawing destination, only the writing operation is required. Therefore, since it is not necessary to read the sketch, the memory access amount can be extremely reduced and high speed operation can be performed. When the drawing unit 23 writes the data, the drawing address and the drawing data are stored in the register file 2800, and the counter 2801 is counted up. When the counter 2801 detects that the register file 2800 is full, the memory controller 3
The write request is output to 0. Again CPU
Similar to the FIFO, the discontinuity of the address to be written in the graphics memory 40 is detected by the disagreement detector 2807, and in the case of discontinuity, the flip-flop 2802 is reset. The bit width to be compared at this time is designated by the MEM bit 320 of the system control register 32. The drawing unit 23 has a function of flushing the data in the cache when one figure drawing command is completed while the cache 328 has a space. When the flush signal becomes active, the cache will activate the counter 28.
Data is written in the graphics memory 40 by the number of words indicated by 01.

A common point of these two is that data is transferred only for the written amount. In a general cache used in a CPU or the like, since writing is performed in line size units, data of a portion that is not rewritten is also transferred. However, the cache described here counts the number of words to be rewritten and eliminates wasteful data transfer (by the counter 252 in FIG. 5).

FIG. 7 shows the operation when the addresses are continuous as described above. When the FIFO is full, the write operation is started and the data is transferred to the memory. The write address at this time is compared with the previous write address stored in the register, and if it is not discontinuous, a write request is set until the end of writing, and transfer to the memory is completed by the number written in the FIFO. Then cancel the write request. As described above, in the case of continuous addresses, 16 words of data can be written in about 20 cycles.

FIG. 8 shows the operation when the addresses are discontinuous. If the write address is discontinuous, a discontinuous signal is set and the write request is canceled once. After that, when the writing of the data before resetting the writing request is completed, the writing request is set again to write the remaining data of the FIFO.

FIG. 9 shows an example of address mapping of the CPU 10. The software of the CPU 10 can access the graphics memory 40 without distinguishing it from the main memory 11. Two frame buffers are provided in the graphics memory area. When displaying a moving image of graphics, these two areas are switched and displayed in units of 1/60 seconds. The drawing unit 23 always draws in the frame buffer which is not being displayed. By doing so, a beautiful moving image can be displayed because the middle of drawing is not displayed. Two display list areas are also provided. Area used by the drawing unit 23 and C
The areas written by the PU 10 are alternately used.

Next, access to the graphics memory 40 by the display controller 24 (hereinafter, this access is referred to as display access) will be described. FIG. 10 is a block diagram of the display controller 24. The display controller 24 sends a synchronization signal (HSYNC, V
SYNC) and display data are output, and a graphic is displayed on the screen of the display 51 (for example, CRT). The timing control unit 246 controls the synchronization signals (HSYNC, VSYNC).
C) is generated, and the output timing of the data in the display buffer 29 is notified to the display data output control 245. The display buffer 29 buffers a part of the data in the display area of the graphics memory 40.
For example, if the display buffer 29 is 128 words, 1
In a system in which the number of pixels is 1 byte, data for 256 pixels is held. Further, it is assumed that the data transfer rate from the graphics memory 40 to the display buffer 29 is sufficiently higher than the data transfer rate from the display buffer 29 to the display 51. For example, the data transfer from the graphics memory 40 to the display buffer 29 is 2
It operates at 8 MHz, and data transfer from the display buffer 29 to the display 51 operates at 14 MHz or less.
Therefore, writing to the display buffer 29 is performed at high speed, and reading from the display buffer 29 is performed at low speed. By doing so, the data transfer timing to the display unit 51 can always be made constant, even if the timing of reading the data to be displayed from the graphics memory 40 is somewhat delayed. The display buffer 29 is controlled as follows.

The display data output control 245 is a display buffer sequentially from the address indicated by the read address register 242 in accordance with the display dot clock (the output of the DCLK terminal of the graphics processor 20 and the clock of one pixel of the display 51). 29 is read and the read address register 242 is updated. On the other hand, the graphics memory access control 240 is activated by a graphics memory access trigger signal, reads the graphics memory 40 by the number of words indicated by the number of continuous access words, and reads the read data in the display buffer 29. The write address register 241 has the function of storing the address. The write address register 241 and the read address register 242 are constantly subtracted by a subtractor 243, and the difference value thereof is compared with a constant by a comparator 244. That is, when the difference value becomes equal to or less than the constant A value (for example, 12 words), the graphics memory access control 240 operates to access the graphics memory 40 and store the display data in the display buffer 29.

FIG. 11 shows the above operation in a time chart. The first operation of display access is initiated by the HSYNC signal. When display access is performed, the number of data words in the display buffer 29 increases. When a certain number of words are accumulated, the display access is interrupted and the display data is transferred to the display unit 51, so that the data gradually decreases. After that, when the number of data becomes equal to or less than the constant A, the access request signal is output to the memory controller 30 again, and the display access is performed again. 320 × 24 per screen
In order to display one screen in the case of 0 dots, display access is performed 1200 times.

The display access delay time (TD) is the time when display access should be started after the access request signal is output. If the display access is not started even after this time is exceeded, the data in the display buffer 29 becomes empty and the screen of the display 51 is disturbed. As described above, the memory controller 30 gives the highest priority to the display access. However, when the display access request comes, C
If another access such as PU is performed, display access is made to wait. Here, if the access period other than display is Ta, it is necessary to always maintain the relationship of Ta <Td.
Therefore, in order to obtain the constant A, it is necessary to determine the maximum time of Ta. In the present embodiment, since the memory is always accessed with consecutive addresses, one access is completed in about 20 cycles. From this, it is possible to easily determine Ta. In the worst case (16
Since the size of the display buffer 29 is determined in consideration of the case where all the words have discontinuous addresses, there is a problem that the buffer size becomes large. However, Ta can be shortened by the present embodiment. It is possible to reduce the size of.

[0059]

According to the present invention, when the graphics processor performs memory access, the buffer size required for display can be made small by always accessing at consecutive addresses, so that the graphics processor is small in size and low in cost. Can be configured.

[Brief description of drawings]

FIG. 1 shows a system configuration example of a graphic processing device.

FIG. 2 shows a terminal function of the graphics processor 20.

FIG. 3 shows a drawing command of the graphics processor 20.

FIG. 4 shows a register function of the graphics processor 20.

FIG. 5 shows a block diagram of a CPU FIFO 25.

FIG. 6 shows a block diagram of cache 3 28.

FIG. 7 shows an example of operation at continuous address.

FIG. 8 shows an example of operation at a discontinuous address.

FIG. 9 shows an example of address mapping of the CPU 10.

FIG. 10 shows an internal block diagram of a display controller.

FIG. 11 shows an example of access contents of a graphics memory.

[Explanation of symbols]

10 ... CPU, 11 ... Main memory, 20 ... Graphics processor, 21 ... CPU I / F, 22 ... Parameter conversion unit, 23 ... Drawing unit, 24 ... Display controller, 25 ... CPU FIFO, 2512 ... Address mismatch detection, 26 ... cache 1 (for command), 27 ... cache 2 (for texture), 28 ... cache 3 (for drawing), 2807 ... address mismatch detection, 29 ... display buffer, 30 ... memory controller, 40 ... graphics memory, 50 ... DAC (Digital to Analog Conver
ter), 51 ... Indicator, 101 ... CPU built-in cache, 320 ... MEM bit.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI G09G 5/36 G09G 5/36 530C 5/393 530E (56) Reference JP-A-10-105154 (JP, A) JP Heihei 10-187118 (JP, A) JP 5-266201 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G09G 5/00-5/42 G06F 3/14-3 / 153 G06F 12/00-12/08 G06T 11/00 100

Claims (4)

(57) [Claims] 1. A CPU for generating drawing procedure information composed of types of graphics figures to be displayed and vertex parameters, a memory for storing the drawing procedure information and bitmap information, and drawing data on the memory. And a graphics processor that sequentially draws a graphic on the memory based on the drawing procedure information, and that further performs display display of the memory to display the bitmap information on the display. The memory is a graphics display device accessed by both the CPU and the graphics processor, and the graphics processor determines whether or not the upper bits of an address to be continuously transferred to the memory are discontinuous. An address detecting unit for detecting the address, and the graphics processor When transferring data to the re-graphics display device characterized by varying the number of transfer of data to the memory by the address discontinuity information detected by the discontinuous address detecting means. 2. The graphics processor according to claim 1, when the address discontinuity information indicates discontinuity, the transfer request from the graphics processor to the memory is canceled once to thereby wasteful arbitration. A graphics display device characterized by saving time and shortening memory access time. 3. The graphics processor according to claim 1, when the address is compared by the discontinuous address detecting means, has information for designating a bit width to be compared according to the type of the memory, and the bit width information. A graphics display device characterized in that the bit width to be compared is changed. 4. A graphic having at least a drawing access for generating bit map information to a memory and a display access for outputting display data to a display, and performing continuous data transfer for each access. In the processor, the graphics processor includes a discontinuity address detecting means for detecting a discontinuity of a part of addresses during data transfer, and the discontinuity address is detected when any one of the access contents is being accessed. A graphics processor, characterized in that, when the continuous address detecting means detects discontinuity, the access is switched to an access other than the access.