KR980006157A - 반도체패키지의 구조 및 제조방법 - Google Patents

반도체패키지의 구조 및 제조방법 Download PDF

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Publication number
KR980006157A
KR980006157A KR1019960022901A KR19960022901A KR980006157A KR 980006157 A KR980006157 A KR 980006157A KR 1019960022901 A KR1019960022901 A KR 1019960022901A KR 19960022901 A KR19960022901 A KR 19960022901A KR 980006157 A KR980006157 A KR 980006157A
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South Korea
Prior art keywords
semiconductor chip
semiconductor package
film
solder ball
circuit pattern
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KR1019960022901A
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English (en)
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KR100231276B1 (ko
Inventor
허영욱
한병준
Original Assignee
황인길
아남산업 주식회사
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Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=19462863&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=KR980006157(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by 황인길, 아남산업 주식회사 filed Critical 황인길
Priority to KR1019960022901A priority Critical patent/KR100231276B1/ko
Priority to US08/763,605 priority patent/US5858815A/en
Priority to JP8353644A priority patent/JP2860646B2/ja
Publication of KR980006157A publication Critical patent/KR980006157A/ko
Application granted granted Critical
Publication of KR100231276B1 publication Critical patent/KR100231276B1/ko

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    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

본 발명은 반도체 패키지의 구조 및 제조방법에 관한 것으로, 반도체패키지의 크기를 기능 저하 없이 반도체칩의 크기로 소형화하고, 고다핀을 실현하면서 경박단소화 한 새로운 형태의 칩 사이즈 패키지(Chip Size Package)로서, 반도체칩의 상면 외측으로 본드패드가 배열되는 타입이나, 반도체칩의 중앙부로 본드패드가 배열되는 타입의 모든 반도체칩을 에리어 어레이(Area Array) 형태로 반도체패키지의 입출력단자를 형성하여 전자제품에 탑재시 그 탑재되는 면적을 최소화하여 제품의 소형화를 가져올 수 있는 것이다.

Description

반도체패키지의 구조 및 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2a도와 제2b도는 본 발명에 의한 반도체패키지의 구조를 나타낸 단면도 및 평면도.

Claims (26)

  1. 전자회로가 집적되어 있고, 이 전자회로의 신호를 외부로 인출하기 위한 본드 패드(Bond Pad)가 형성된 반도체칩과, 상기 반도체칩의 상면에 본드패드를 제외한 영역에 접착수단에 의해서 부착되며, 내부에는 도전체의 회로패턴이 형성되고, 그 양면에 코팅된 비전도성 필름과, 상기 반도체칩의 본드패드와 회로패턴과의 신호를 전달하기 위하여 연결된 와이어와, 상기 와이어가 본딩된 영역을 외부의 산화 및 부식으로부터 보호하기 위한 봉지재와, 상기 와이어에 의해 전달된 반도체칩의 신호를 외부로 인출하기 위하여 회로패턴에 융착되어 있는 솔더볼로 이루어지는 것을 특징으로 하는 반도체패키지.
  2. 제1항에 있어서, 상기 반도체칩에 형성된 본드패드는 반도체칩의 상면 외측으로 배열되어 있는 것을 특징으로 하는 반도체패키지.
  3. 제1항에 있어서, 상기 반도체칩에 형성된 본드패드는 반도체칩의 상면 중앙부에 배열되어 있는 것을 특징으로 하는 반도체패키지.
  4. 제1항에 있어서, 상기 비전도성 필름은 제1 필름 위에 도전체로 회로패턴을 형성하고, 그 위에 제2 필름을 라미레이션(Lamination)시켜서 형성된 것을 특징으로 하는 반도체패키지.
  5. 제4항에 있어서, 상기 회로패턴은 20㎛ 이하의 두께를 갖는 도전체로 이루어 진 것을 특징으로 하는 반도체패키지.
  6. 제4항에 있어서, 상기 제2 필름은 솔더볼이 회로패턴에 융착되는 솔더볼 랜드의 영역이 오픈되고, 상기 와이어가 본딩되는 본드핑거의 영역이 오픈되어 있는 것을 특징으로 하는 반도체패키지.
  7. 제6항에 있어서, 상기 솔더볼 랜드는 제2 필름의 상면에 어레이(Array)형 태로 배열된 것을 특징으로 하는 반도체패키지.
  8. 제1항 또는 제4항에 있어서, 상기 비전도성 필름은 폴리머 테이프(Polymer Tape)나, 폴리이미드(Polyimide)의 재질로 된 것을 특징으로 하는 반도체패키지.
  9. 제1항 또는 제4항에 있어서, 상기 회로패턴은 카퍼 포일(Copper Foil)이나, 컨닥터(Conductor)의 재질로 된 것을 특징으로 하는 반도체패키지.
  10. 제1항 또는 제6항에 있어서, 상기 솔더볼 랜드와 본드핑거에는 니켈(Ni) 또는 금(Gold)이 도금된 것을 특징으로 하는 반도체패키지.
  11. 제1항에 있어서, 상기 반도체칩의 상면에 비전도성 필름을 부착시키는 접착수단은 에폭시 어드히시브(Epoxy Adhesive) 또는 어드히시브 필름(Adhesive Film)으로 된 것을 특징으로 하는 반도체패키지.
  12. 제1항에 있어서, 상기 봉지재는 에폭시(Epoxy), 폴리이미드(Polyimide)의 코팅(Coating)용액, 에폭시 타입(Epoxy Type)의 인캡슐레이션 머틸리얼(Encapsu lati on Material)로 된 것을 특징으로 하는 반도체패키지.
  13. 반도체칩의 원자재로서 각각의 반도체칩에는 전자회로가 접적되어 있고, 이 전자회로의 신호를 외부로 인출하기 위한 본드패드(Bond Pad)가 각각의 반도체칩에 형성되어 있는 웨이퍼(Wafer)를 형성하는 단계와, 상기 웨이퍼와 동일한 크기로 형성되며, 두개의 층(Layer)으로 이루어지고, 그 사이에 도전체의 회로패턴이 형성되며, 상기 반도체칩의 본드패드가 위치되는 영역에는 개방부가 형성되는 비전도성 필름을 형성하는 단계와, 상기 웨이퍼의 각각의 반도체칩에 형성된 본드패드의 영역이 상기 비전도성 필름의 개방부를 통해 외부로 노출되도록 상기 웨이퍼와 상기 비전도성 필름을 접착수단에 의해 서로 부착하는 단계와, 상기 웨이퍼의 각각의 반도체칩에 형성된 본드패드와 비전도성 필름의 회로패턴에 형성된 본드핑거를 와이어로 본딩하는 단계와, 상기 와이어를 외부의 산화 및 부식으로부터 보호하기 위하여 상기 개방부를 봉지재로 덮어 씌우는 단계와, 상기 봉지재를 150℃ 이상의 오븐(Oven) 또는, 퍼니스(Furnace)에서 경화시키는 단계와, 상기 비전도성 필름의 솔더볼 랜드에 솔더볼을 안측시켜 220℃ 이상의 고온을 유지하는 오븐(Oven) 또는 퍼니스(Furnace)에서 상기 솔더볼을 리플로우하여 회로패턴에 솔더볼을 융착시키는 단계와, 상기 단계를 거친 후에, 소잉(Sawing)장비를 이용하여 웨이퍼의 스트리트 라인(Street Line)을 따라 반도체칩을 절단하여 반도체칩의 크기와 동일한 크기의 칩 사이즈 패키지(Chip Size Package)를 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체패키지의 제조방법.
  14. 제13항에 있어서, 상기 웨이퍼의 각각의 반도체칩에 형성된 본드패드는 각각의 반도체칩의 상면 외측으로 배열되어 있는 것을 특징으로 하는 반도체패키지의 제조방법.
  15. 제13항에 있어서, 상기 웨이퍼의 각각의 반도체칩에 형성된 본드패드는 각각의 반도체칩의 상면 중앙부로 배열되어 있는 것을 특징으로 하는 반도체패키지의 제조방법.
  16. 제13항에 있어서, 상기 두개의 층으로 이루어진 비전도성 필름은 하부의 제1 필름 위에 도전체로서 원하는 형태의 회로패턴을 형성한 후, 그 위에 제2 필름을 라미레이션(Lamination)시켜서 형성하는 것을 특징으로 하는 반도체패키지의 제조방법.
  17. 제16항에 있어서, 상기 제2 필름에는 솔더볼이 회로패턴에 융착될 수 있는 솔더볼 랜드가 오픈되게 형성되고, 상기 반도체칩의 본드패드와 와이어로 연결되는 본드핑거가 오픈되도록 형성되는 것을 특징으로 하는 반도체패키지의 제조방법.
  18. 제17항에 있어서, 상기 솔더볼랜드는 제2 필름의 상면에 어레이(Array)형태로 배열되고, 상기 본드핑거는 제2 필름의 개방부 외측으로 형성됨을 특징으로 하는 반도체패키지의 제조방법.
  19. 제16항에 있어서, 상기 회로패턴은 두께가 20㎛ 이하의 도전체로 이루어지는 것을 특징으로 하는 반도체패키지의 제조방법.
  20. 제13항에 있어서, 상기 접착수단은 에폭시어드히시브(Epoxy Adhesive) 또는 어드히시브 필름(Adhesive Film)을 사용하는 것을 특징으로 하는 반도체패키지의 제조방법.
  21. 제13항에 있어서, 상기 봉지재는 에폭시(Epoxy) 또는 폴리이미드(Polyimide)의 코팅(Coating)용액을 사용하거나, 또는 에폭시 타입(Epoxy Type)의 인캡슐레이션 머틸리얼(Encapsulation Material)을 이용하여 와이어가 노출되지 않도록 개방부를 덮어 씌우는 것을 특징으로 하는 반도체패키지의 제조방법.
  22. 제13항에 있어서, 상기 솔더볼을 형성하는 단계는 솔더볼 랜드와 대응하는 관통공이 형성된 스텐슬 스크린 프린터(Stencil Screen Print)를 비전도성 필름 위에 위치시킨 상태에서 솔더 파우더(Sclder Powder)를 블레이드(Blade)로 밀어서 상기 관통공을 통해 솔더볼 랜드로 솔더 파우더가 삽입되도록 한 다음, 220℃ 이상의 고온을 유지하는 오븐(Oven) 또는, 퍼니스(Furnace)에서 리플로우하여 솔더볼랜드를 통해 회로기판과 융착시켜 솔더볼을 형성화하는 것을 특징으로 하는 반도체패키지의 제조방법.
  23. 제22항에 있어서, 상기 스텐슬 스크린 프린터는 비전도성 필름의 개방부에 봉지재가 채워진 영역이 위치되는 저면에 홈을 형성하여 상기 봉지재를 보호하도록 하는 것을 특징으로 하는 반도체패키지의 제조방법.
  24. 제13항에 있어서, 상기 솔더볼 랜드에 안착되는 솔더볼은 미리 구형으로 만들어진 솔더볼을 사용하는 것을 특징으로 하는 반도체패키지의 제조방법.
  25. 제13항에 있어서, 상기 솔더볼 랜드에 솔더볼을 융착할 때 플럭스(Flux)를 도포하여 리플로우시켜 솔더볼을 형성하는 단계 후에 불필요한 플럭스의 잔조물을 제거하기 위하여 클리닝(Clearing)단계를 포함하는 것을 특징으로 하는 반도체패키지의 제조방법.
  26. 제13항에 있어서, 상기 비전도성 필름에 형성된 회로패턴은 다수의 회로라인을 서로 연결되어 파워 본딩(Power Bonding)이나, 그라운드 본딩(Ground Bonding)으로 사용하는 것을 특징으로 하는 반도체패키지의 제조방법.
KR1019960022901A 1996-06-21 1996-06-21 반도체패키지의 구조 및 제조방법 KR100231276B1 (ko)

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KR1019960022901A KR100231276B1 (ko) 1996-06-21 1996-06-21 반도체패키지의 구조 및 제조방법
US08/763,605 US5858815A (en) 1996-06-21 1996-12-11 Semiconductor package and method for fabricating the same
JP8353644A JP2860646B2 (ja) 1996-06-21 1996-12-17 半導体パッケージ及び製造方法

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KR1019960022901A KR100231276B1 (ko) 1996-06-21 1996-06-21 반도체패키지의 구조 및 제조방법

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