KR970072363A - Bga 반도체 패키지의 pcb 기판 구조 - Google Patents

Bga 반도체 패키지의 pcb 기판 구조 Download PDF

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Publication number
KR970072363A
KR970072363A KR1019960009779A KR19960009779A KR970072363A KR 970072363 A KR970072363 A KR 970072363A KR 1019960009779 A KR1019960009779 A KR 1019960009779A KR 19960009779 A KR19960009779 A KR 19960009779A KR 970072363 A KR970072363 A KR 970072363A
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South Korea
Prior art keywords
solder mask
pcb substrate
thickness
substrate structure
capa
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KR1019960009779A
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English (en)
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KR100197877B1 (ko
Inventor
김영문
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황인길
아남산업 주식회사
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Priority to KR1019960009779A priority Critical patent/KR100197877B1/ko
Publication of KR970072363A publication Critical patent/KR970072363A/ko
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Publication of KR100197877B1 publication Critical patent/KR100197877B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

본 발명은 BGA 반도체 패키지의 PCB 기판 구조에 관한 것으로, 본 발명에 의한 PCB 기판의 제조 개념은 BT 섭스트레이트 중앙 상면에 형성된 솔더 마스크의 두께와 BT 섭스트레이트의 상면 외곽에 형성된 솔더 마스크의 두께를 다르게 형성하는 것으로 반도체 칩이 접착될 부위인 BT 섭스트레이트의 중앙 상면에 형성된 카파 트레이스의 표면에는 솔더 레지스트로1회 도포 작업을 실시하거나, 산화처리하고 그 외의 부위, 즉 BT 섭스트레이트의 상면 외곽에 형성된 카파 트레이스의 표면에는 종전과 같이 2회 도포 작업을 실시함으로서 반도체 칩이 접착될 솔더 마스크의 두께는 20~35㎛를 유지하고, 그 외의 솔더 마스크는 종전과 같이 40~75㎛의 두께로 형성시킴으로서 에폭시를 이용한 반도체 접착 작업에서 에폭시가 댐을 타고 넘치는 현상을 최소화하고 따라서 그라운드에 대한 다운 본딩의 신뢰성이 향상되고 또한 PCB기판의 휨 현상을 개선하여 에폭시 보이드나 반도체 칩의 크랙 현상을 최소화할 수 있는 것이다.

Description

BGA 반도체 패키지의 PCB 기판 구조
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명에 따른 PCB 기판의 구조를 나타낸 단면도.

Claims (4)

  1. 저면 전체에 카파 트레이스와 솔더 마스크가 형성된 BT 섭스트레이트와, 상기 BT 섭스트레이트의 상면 중앙에 형성된 카파트레이스와, 상기 카파 트레이스의 외곽에 형성된 댐과, 상기 카파 트레이스의 표면에 1회 도포하여 형성된 솔더 마스크와, 상기 BT섭스트레이트의 상면 외곽으로 형성된 카파 트레이스와, 상기 카파 트레이스의 표면에 2회 도포하여 형성된 솔더 마스크로 이루어짐을 특징으로 하는 BGA 반도체 패키지의 PCB 기판구조.
  2. 제1항에 있어서, 상기 댐의 높이는 BT 섭스트레이트 중앙 상면에 형성된 솔더 마스크의 높이보다 더 높음을 특징으로 하는 BGA 반도체 패키지의 PCB 기판 구조.
  3. 제1항에 있어서, 1회 도포하여 형성된 솔더 마스크의 두께20~35㎛임을 특징으로 하는 BGA 반도체 패키지의 PCB 기판구조.
  4. 제1항에 있어서, 상기 BT 섭스트레이트의 중앙 상면에 형성된 카파트레이스의 표면에는 산화막을 형성하고 솔'더 마스크를 도포하지 않음을 특징으로 하는 BGA 반도체 패키지의 PCB 기판 구조.
    ※ 참고사항: 최초출원 내용에 의하여 공개하는 것임.
KR1019960009779A 1996-04-01 1996-04-01 Bga 반도체 패키지의 pcb 기판 구조 KR100197877B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960009779A KR100197877B1 (ko) 1996-04-01 1996-04-01 Bga 반도체 패키지의 pcb 기판 구조

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960009779A KR100197877B1 (ko) 1996-04-01 1996-04-01 Bga 반도체 패키지의 pcb 기판 구조

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KR970072363A true KR970072363A (ko) 1997-11-07
KR100197877B1 KR100197877B1 (ko) 1999-06-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100370852B1 (ko) * 1999-12-20 2003-02-05 앰코 테크놀로지 코리아 주식회사 반도체패키지

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030091519A (ko) * 2002-05-28 2003-12-03 삼성전기주식회사 접지와이어 본딩 벽을 갖는 파워 앰프 모듈 및 파워 앰프모듈 기판 제조방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100370852B1 (ko) * 1999-12-20 2003-02-05 앰코 테크놀로지 코리아 주식회사 반도체패키지

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