KR970024042A - 관통슬롯 둘레에 에폭시 배리어가 형성된 기판 및 이를 이용한 향상된 습기 방출특성을 갖는 볼 그리드 어레이 - Google Patents

관통슬롯 둘레에 에폭시 배리어가 형성된 기판 및 이를 이용한 향상된 습기 방출특성을 갖는 볼 그리드 어레이 Download PDF

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KR970024042A
KR970024042A KR1019950037513A KR19950037513A KR970024042A KR 970024042 A KR970024042 A KR 970024042A KR 1019950037513 A KR1019950037513 A KR 1019950037513A KR 19950037513 A KR19950037513 A KR 19950037513A KR 970024042 A KR970024042 A KR 970024042A
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pcb substrate
package structure
attached
semiconductor package
epoxy
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KR1019950037513A
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KR0170024B1 (ko
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하선호
허영욱
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황인길
아남산업 주식회사
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Priority to KR1019950037513A priority Critical patent/KR0170024B1/ko
Priority to US08/736,107 priority patent/US5767446A/en
Priority to JP8302542A priority patent/JP2899958B2/ja
Publication of KR970024042A publication Critical patent/KR970024042A/ko
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Publication of KR0170024B1 publication Critical patent/KR0170024B1/ko

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Abstract

본 발명은 BGA 반도체 패키지 구조에 관한 것으로, 반도체 칩이 부착되는 부분의 PCB기판에 형성된 열방출용 구멍 주변에 홈 또는 댐을 형성하여 에폭시를 도포시 상기 구멍으로 에폭시가 누출되는 것을 방지하고, 고온의 제조 공정중 반도체 칩과 PCB기판과의 계면에서 발생되는 박리 및 패키지의 크랙을 방지하여 패키지의 신뢰성을 향상시킨 BGA 반도체 패키지 구조이다.

Description

관통슬롯 둘레에 에폭시 배리어가 형성된 기판 및 이를 이용한 향상된 습기 방출특성을 갖는 볼 그리드 어레이
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 3A 도 내지 제 3B 도는 본 발명에 따른 제 1 실시예를 도시한 BGA 반도체 패키지의 단면도,
제 4 도는 본 발명에 따른 제 2 실시예를 도시한 BGA 반도체 패키지의 단면도.

Claims (4)

  1. 구리층과 솔더레지스트층이 도포된 PCB기판의 저면에는 다수의 솔더볼이 부착되고, 상부에는 반도체 칩이 에폭시에 의해 부착되며, 상기 반도체 칩이 부착된 부위의 PCB기판에는 구멍이 형성되고, 상기 반도체 칩과 PCB기판 상에는 와이어로 본딩되며, 그 외부는 컴파운드 몰딩된 BGA 반도체 패키지 구조에 있어서, 상기 PCB 기판에 형성된 구멍의 주변에 홈을 형성하여서 된 것을 특징으로 하는 BGA 반도체 패키지 구조.
  2. 제 1 항에 있어서, 상기 홈은 솔더레지스트층과 구리층을 파내서 형성한 것을 특징으로 하는 BGA 반도체 패키지 구조.
  3. 제 1 항에 있어서, 상기 홈은 솔더레지스트층을 파내서 형성한 것을 특징으로 하는 BGA 반도체 패키지 구조.
  4. 구리층과 솔더레지스트층이 도포된 PCB기판의 저면에는 다수의 솔더볼이 부착되고, 상부에는 반도체 칩이 에폭시에 의해 부착되며, 상기 반도체 칩이 부착된 부위의 PCB기판에는 구멍이 형성되고, 상기 반도체 칩과 PCB기판 상에는 와이어로 본딩되며, 그 외부는 컴파운드 몰딩된 BGA 반도체 패키지 구조에 있어서, 상기 PCB 기판에 형성된 구멍의 주변에 댐을 형성하여서 된 것을 특징으로 하는 BGA 반도체 패키지 구조.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950037513A 1995-10-27 1995-10-27 관통 슬롯 둘레에 에폭시 배리어가 형성된 기판 및 이를 이용한 향상된 습기 방출 특성을 갖는 볼 그리드 어레이 반도체 패키지 KR0170024B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019950037513A KR0170024B1 (ko) 1995-10-27 1995-10-27 관통 슬롯 둘레에 에폭시 배리어가 형성된 기판 및 이를 이용한 향상된 습기 방출 특성을 갖는 볼 그리드 어레이 반도체 패키지
US08/736,107 US5767446A (en) 1995-10-27 1996-10-24 Printed circuit board having epoxy barrier around a throughout slot and ball grid array semiconductor package
JP8302542A JP2899958B2 (ja) 1995-10-27 1996-10-28 エポキシバリヤーが形成された基板及びこれを用いた半導体パッケージ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950037513A KR0170024B1 (ko) 1995-10-27 1995-10-27 관통 슬롯 둘레에 에폭시 배리어가 형성된 기판 및 이를 이용한 향상된 습기 방출 특성을 갖는 볼 그리드 어레이 반도체 패키지

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KR970024042A true KR970024042A (ko) 1997-05-30
KR0170024B1 KR0170024B1 (ko) 1999-02-01

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Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6489668B1 (en) * 1997-03-24 2002-12-03 Seiko Epson Corporation Semiconductor device and method for manufacturing the same
US6509807B1 (en) 1997-04-08 2003-01-21 X2Y Attenuators, Llc Energy conditioning circuit assembly
US6606011B2 (en) 1998-04-07 2003-08-12 X2Y Attenuators, Llc Energy conditioning circuit assembly
US7321485B2 (en) 1997-04-08 2008-01-22 X2Y Attenuators, Llc Arrangement for energy conditioning
US9054094B2 (en) 1997-04-08 2015-06-09 X2Y Attenuators, Llc Energy conditioning circuit arrangement for integrated circuit
US6650525B2 (en) 1997-04-08 2003-11-18 X2Y Attenuators, Llc Component carrier
US7336468B2 (en) 1997-04-08 2008-02-26 X2Y Attenuators, Llc Arrangement for energy conditioning
US7301748B2 (en) 1997-04-08 2007-11-27 Anthony Anthony A Universal energy conditioning interposer with circuit architecture
US6995983B1 (en) 1997-04-08 2006-02-07 X2Y Attenuators, Llc Component carrier
JP3147053B2 (ja) * 1997-10-27 2001-03-19 日本電気株式会社 樹脂封止型ボールグリッドアレイｉｃパッケージ及びその製造方法
US6495083B2 (en) 1997-10-29 2002-12-17 Hestia Technologies, Inc. Method of underfilling an integrated circuit chip
US6324069B1 (en) 1997-10-29 2001-11-27 Hestia Technologies, Inc. Chip package with molded underfill
US6038136A (en) * 1997-10-29 2000-03-14 Hestia Technologies, Inc. Chip package with molded underfill
SG73490A1 (en) * 1998-01-23 2000-06-20 Texas Instr Singapore Pte Ltd High density internal ball grid array integrated circuit package
US6080932A (en) * 1998-04-14 2000-06-27 Tessera, Inc. Semiconductor package assemblies with moisture vents
US6404067B1 (en) 1998-06-01 2002-06-11 Intel Corporation Plastic ball grid array package with improved moisture resistance
US6208524B1 (en) * 1998-07-23 2001-03-27 Micron Technology, Inc. Electronic apparatus, battery powerable apparatus, and radio frequency communication device
JP2000294894A (ja) * 1998-12-21 2000-10-20 Seiko Epson Corp 回路基板およびその製造方法ならびに回路基板を用いた表示装置および電子機器
JP3914654B2 (ja) * 1999-03-17 2007-05-16 株式会社ルネサステクノロジ 半導体装置
US6199464B1 (en) 1999-07-12 2001-03-13 Lucent Technologies, Inc. Method and apparatus for cutting a substrate
JP2001326304A (ja) * 2000-05-15 2001-11-22 Toshiba Corp 半導体装置及びその製造方法
US6589820B1 (en) 2000-06-16 2003-07-08 Micron Technology, Inc. Method and apparatus for packaging a microelectronic die
DE10035399A1 (de) * 2000-07-19 2002-01-31 Alcatel Sa Subträger, elektronische Baugruppe und Verfahren zur Herstellung derselben
US6483044B1 (en) * 2000-08-23 2002-11-19 Micron Technology, Inc. Interconnecting substrates for electrical coupling of microelectronic components
US6979595B1 (en) * 2000-08-24 2005-12-27 Micron Technology, Inc. Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectronic devices
US6838760B1 (en) 2000-08-28 2005-01-04 Micron Technology, Inc. Packaged microelectronic devices with interconnecting units
KR100386634B1 (ko) * 2000-12-29 2003-06-02 앰코 테크놀로지 코리아 주식회사 비지에이 패키지용 기판의 습기 배출공 형성방법
KR100774840B1 (ko) * 2001-02-02 2007-11-07 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
US20030205828A9 (en) * 2001-04-05 2003-11-06 Larry Kinsman Circuit substrates, semiconductor packages, and ball grid arrays
US6773964B2 (en) * 2002-09-30 2004-08-10 Koninklijke Philips Electronics N.V. Integrated circuit package including sealed gaps and prevention of vapor induced failures and method of manufacturing the same
US7675729B2 (en) 2003-12-22 2010-03-09 X2Y Attenuators, Llc Internally shielded energy conditioner
GB2439862A (en) 2005-03-01 2008-01-09 X2Y Attenuators Llc Conditioner with coplanar conductors
WO2006093831A2 (en) 2005-03-01 2006-09-08 X2Y Attenuators, Llc Energy conditioner with tied through electrodes
US20060261498A1 (en) * 2005-05-17 2006-11-23 Micron Technology, Inc. Methods and apparatuses for encapsulating microelectronic devices
EP1991996A1 (en) 2006-03-07 2008-11-19 X2Y Attenuators, L.L.C. Energy conditioner structures
JP2008016630A (ja) * 2006-07-06 2008-01-24 Matsushita Electric Ind Co Ltd プリント配線板およびその製造方法
US7833456B2 (en) * 2007-02-23 2010-11-16 Micron Technology, Inc. Systems and methods for compressing an encapsulant adjacent a semiconductor workpiece
JP5272191B2 (ja) * 2007-08-31 2013-08-28 三菱電機株式会社 半導体装置および半導体装置の製造方法
KR101008399B1 (ko) * 2007-09-03 2011-01-14 주식회사 비에스이 내벽을 금속성 혹은 전도성 물질로 감싼 세라믹 패키지를이용한 콘덴서 마이크로폰
KR101043643B1 (ko) * 2008-02-22 2011-06-24 주식회사 바른전자 접합용 구조물 및 이를 이용한 기판 접합 방법
KR101902996B1 (ko) 2012-07-09 2018-10-01 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
US9030000B2 (en) * 2013-06-14 2015-05-12 Freescale Semiconductor, Inc. Mold cap for semiconductor device
JP2016207952A (ja) * 2015-04-28 2016-12-08 富士通株式会社 部品内蔵基板
CN113658923A (zh) * 2020-05-12 2021-11-16 宇瞻科技股份有限公司 封装结构

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0423485A (ja) * 1990-05-18 1992-01-27 Cmk Corp プリント配線板とその製造法
US5120678A (en) * 1990-11-05 1992-06-09 Motorola Inc. Electrical component package comprising polymer-reinforced solder bump interconnection
US5612576A (en) * 1992-10-13 1997-03-18 Motorola Self-opening vent hole in an overmolded semiconductor device

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