KR970067732A - 접착 조성물의 수축으로 인한 파손이 적은 반도체 칩과 기판 사이의 전기적 접속을 갖는 반도체 소자 및 그 실장 방법 - Google Patents

접착 조성물의 수축으로 인한 파손이 적은 반도체 칩과 기판 사이의 전기적 접속을 갖는 반도체 소자 및 그 실장 방법 Download PDF

Info

Publication number
KR970067732A
KR970067732A KR1019970007700A KR19970007700A KR970067732A KR 970067732 A KR970067732 A KR 970067732A KR 1019970007700 A KR1019970007700 A KR 1019970007700A KR 19970007700 A KR19970007700 A KR 19970007700A KR 970067732 A KR970067732 A KR 970067732A
Authority
KR
South Korea
Prior art keywords
composition layer
adhesive composition
circuit component
electrical circuit
semiconductor device
Prior art date
Application number
KR1019970007700A
Other languages
English (en)
Other versions
KR100244047B1 (ko
Inventor
후또시 나까니시
Original Assignee
가네꼬 히사시
닛뽕덴끼 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가네꼬 히사시, 닛뽕덴끼 가부시끼가이샤 filed Critical 가네꼬 히사시
Publication of KR970067732A publication Critical patent/KR970067732A/ko
Application granted granted Critical
Publication of KR100244047B1 publication Critical patent/KR100244047B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Materials Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Combinations Of Printed Boards (AREA)
  • Die Bonding (AREA)

Abstract

접착 조성물층 (12) 은 반도체 칩 (10) 의 반대측면을 기판 (11)의 주 표면에 접착시키고, 복원 조성물층(13) 은 반도체 칩의 상면에 형성시켜, 제 1 힘에 기인하는 제 1 모멘트 (M1) 가 제 2 힘 (F2) 에 기인하는 제 2 모멘트 (M2)에 의해서 감소 또는 상쇄되도록, 접착 조성물층 및 복원 조성물층이 열경화되는 동안 수축하는데 기인하는 반대측면에 제 1 힘 (F1) 및 상면 상에 제 2 힘 (F2) 을 인가함으로서, 반도체 칩의 바람직하지 않은 휨을 방지한다.

Description

접착 조성물의 수축으로 인한 파손이 적은 반도체 칩과 기판 사이의 전기적 접속을 갖는 반도체 소자 및 그 실장 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
도 3은 본 발명에 따른 반도체 소자의 구조를 도시한 단면도.

Claims (12)

  1. 표면을 갖는 절연판 (11a) 및 상기 절연판의 상기 표면상에 형성된 한 개 이상의 도체 배선 (11b/11c)을 갖는 기판(11;21), 제 1표면, 상기 제 1표면의 반대측의 제 2표면, 및 상기 제 1표면상에 형성되어 한 개 이상의 상기 도체 배선과 접촉하는 한 개 이상의 전극 (10a/10b) 을 갖는 전기 회로 부품 (10;20), 및 상기 전기 회로 부품을 상기 기판에 접착하기 위해 기판의 제 1표면과 상기 전기 부품의 상기 제 1표면 사이에 형성되어, 경화되는 동안 수축에 의해 상기 전기회로 부품의 상기 제 1표면에 상기 제 1힘 (F1)을 인가하는 경화된 접착조성물 (12;22)을 구비하는 반도체 소자에 있어서, 상기 전기회로 부품의 상기 제 2표면상에 복원 조성물층 (13;24)을 형성하여 그 수축에 의해 상기 전기 부품의 상기 제2표면상에 제2힘을 인가함으로서, 상기 전기 회로 부품의 상기 제 1표면상에 인가되는 상기 제 1힘에 기인하는 모멘트를 감소시키는 것을 특징으로 하는 반도체 소자.
  2. 제1항에 있어서, 상기 경화된 접착조성물 및 상기 복원 조성물층을 위한 조성물이 에폭시 시스템의 합성 수지인 것을 특징으로 하는 반도체 소자.
  3. 제1항에 있어서, 상기 합성 수지가 가열에 의해 경화되는 것을 특징으로 하는 반도체 소자.
  4. 제1항에 있어서, 상기 경화된 접착조성물 및 상기 복원 조성물층을 위한 조성물이 에폭시 시스템의 합성 수지이고, 서로의 두께가 거의 같은 것을 특징으로 하는 반도체 소자.
  5. 제1항에 있어서, 바람직하게는 상기 전기 회로 부품의 상기 제 2표면에 접촉하고 상기 복원 조성물층 (24)에 의해 상기 전기 회로 부품에 접착된 히트 싱크(23)를 더 구비하는 것을 특징으로 하는 반도체소자.
  6. a)주 표면상에 한 개 이상의 도체층(11b/11c)으로 형성된 기판(11;21), 상기 주표면 상에 형성된 접착 조성물층(15;30), 전기 회로 부품의 반대측면으로부터 돌출되어 상기 접착 조성물층을 통해 한 개 이상의 상기 도체층에 대향하는 한 개 이상의 전극을 갖는 전기 회로 부품(10;20), 및 상기 전기 회로 부품의 상면에 형성된 복원 조성물층(13;31)을 갖는 중간 구조물을 준비하는단계,
    b)상기 한 개 이상의 전극을 한 개 이상의 도체 층에 접촉하도록 상기 접착 조성물층르로 상기 전기 회로 부품을 누르는 단계, 및
    c)상기 전기 회로 부품을 상기 기판에 고착하기 위해 적어도 상기 접착 조성물층을 경화시키는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 실장 방법.
  7. 제6항에 있어서, a)단계가
    a-1)상기 전기 회로부품(10)을 준비하는 단계,
    a-2)상기 복원 조성물층(13)으로 상기 전기 회로부품의 상기 상면을 코팅하는 단계,
    a-3)상기 접착 조성물층 (15)으로 상기 기판(11)의 상기 주 표면을 코팅하는 단계 및
    a-4)한 개 이상의 상기 도체층과 한 개 이상의 전극을 정렬시키는 방식으로 상기 접착 조성물층에 상기 전기 회로부품(10)을 위치시키는 단계인 서브 단계를 포함하는 것을 특징으로 하는 반도체 소자의 살장방법.
  8. 제6항에 있어서, 상기 접착 조성물층(15;30)이 가열에 의해 경화되는 것을 특징으로 하는 반도체 소자의 실장 방법.
  9. 제8항에 있어서, 접착 조성물층(15)은 제1온도에서 경화되고, 상기 복원 조성물층 (13)은 상기 제 1온도 보다 낮은 제2온도에서 부드러워지는 것을 특징으로 하는 반도체 소자의 실장방법.
  10. 제9항에 있어서, 열이 상기 복원 조성물층(13)을 통해 상기 접착 조성물층 (15)에 인가되는 것을 특징으로 하는 반도체 소자의 실장 방법.
  11. 제6항에 있어서, 상기 a)단계가
    a-1) 상기 기판(21)을 준비하는 단계,
    a-2)상기 접착 조성물층 (30)으로 상기 기판의 상기 주 표면을 코팅하는 단계,
    a-3)한 개의 이상의 상기 도체층과 한 개 이상의 전극을 정렬시키는 방식으로 상기 접착 조성물층 상에 상기 전기회로 부품을 위치시키는 단계,
    a-4) 상기 복원 조성물층(31)으로 상기 상면을 코팅하는 단계, 및
    a-5) 상기 복원 조성물층에 히트 싱크(23)를 위치시키는 단계인 서브 단계를 포함하고,
    상기 전기회로 부품(20) 은, 한 개 이상의 상기 전극 및 상기 히트 싱크가 상기 접착 조성물층 및 상기 복원 조성물층으로 하강 하도록 상기 히트 싱크(23)를 통해 상기 접착 조성물층으로 각각 눌려지는 것을 특징으로 하는 반도체 소자의 실장방법.
  12. 제11항에 있어서, 상기 복원 조성물층이 상기 c)단계에서 동시에 경화되는 것을 특징으로 하는 반도체 소자의 실장 방법.
KR1019970007700A 1996-03-08 1997-03-07 접착 조성물의 수축으로 인한 파손이 적은 반도체 칩과 기판 사이의 전기적 접속을 갖는 반도체 소자 및 그 실장 방법 KR100244047B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP9651614 1996-03-08
JP8051614A JP2806348B2 (ja) 1996-03-08 1996-03-08 半導体素子の実装構造及びその製造方法
JP96-51614 1996-03-08

Publications (2)

Publication Number Publication Date
KR970067732A true KR970067732A (ko) 1997-10-13
KR100244047B1 KR100244047B1 (ko) 2000-02-01

Family

ID=12891781

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970007700A KR100244047B1 (ko) 1996-03-08 1997-03-07 접착 조성물의 수축으로 인한 파손이 적은 반도체 칩과 기판 사이의 전기적 접속을 갖는 반도체 소자 및 그 실장 방법

Country Status (4)

Country Link
US (1) US5895971A (ko)
JP (1) JP2806348B2 (ko)
KR (1) KR100244047B1 (ko)
TW (1) TW352450B (ko)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1041694A (ja) * 1996-07-25 1998-02-13 Sharp Corp 半導体素子の基板実装構造及びその実装方法
JP3702788B2 (ja) * 1998-07-01 2005-10-05 セイコーエプソン株式会社 半導体装置の製造方法
US6730998B1 (en) * 2000-02-10 2004-05-04 Micron Technology, Inc. Stereolithographic method for fabricating heat sinks, stereolithographically fabricated heat sinks, and semiconductor devices including same
US6502926B2 (en) 2001-01-30 2003-01-07 Lexmark International, Inc. Ink jet semiconductor chip structure
JP4714026B2 (ja) * 2006-01-10 2011-06-29 株式会社東芝 電子部品実装装置、電子部品実装方法及び電子部品装置
KR20090044636A (ko) * 2007-11-01 2009-05-07 삼성전자주식회사 반도체 칩 패키지 및 그의 형성방법
JP5088489B2 (ja) * 2008-03-03 2012-12-05 セイコーエプソン株式会社 半導体モジュール及びその製造方法
JP5533199B2 (ja) * 2010-04-28 2014-06-25 ソニー株式会社 素子の基板実装方法、および、その基板実装構造
CN114746988A (zh) * 2019-12-04 2022-07-12 3M创新有限公司 包括微图案并使用部分固化以粘附管芯的电路

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0671028B2 (ja) * 1988-07-19 1994-09-07 松下電器産業株式会社 半導体素子の実装方法
JP3150351B2 (ja) * 1991-02-15 2001-03-26 株式会社東芝 電子装置及びその製造方法
JPH05235063A (ja) * 1992-02-21 1993-09-10 Nippon Steel Corp 半導体装置
CA2157148A1 (en) * 1994-09-08 1996-03-09 Masatsugu Akiba Epoxy resin composition and resin-encapsulated semiconductor device
KR0181615B1 (ko) * 1995-01-30 1999-04-15 모리시다 요이치 반도체 장치의 실장체, 그 실장방법 및 실장용 밀봉재
US5627407A (en) * 1995-04-28 1997-05-06 Lucent Technologies Inc. Electronic package with reduced bending stress

Also Published As

Publication number Publication date
US5895971A (en) 1999-04-20
JP2806348B2 (ja) 1998-09-30
JPH09246325A (ja) 1997-09-19
KR100244047B1 (ko) 2000-02-01
TW352450B (en) 1999-02-11

Similar Documents

Publication Publication Date Title
US5448450A (en) Lead-on-chip integrated circuit apparatus
US6881071B2 (en) Power semiconductor module with pressure contact means
US5221642A (en) Lead-on-chip integrated circuit fabrication method
JP2596960B2 (ja) 接続構造
KR960009074A (ko) 반도체 장치 및 그 제조방법
CN1121062C (zh) 一种装配半导体元件到衬底上的方法
US3615946A (en) Method of embedding semiconductor chip within a dielectric layer flush with surface
JPH09505444A (ja) 接着シートを用いたマルチチップ電子パッケージモジュール
EP0645812B1 (en) Resin-sealed semiconductor device
KR970067732A (ko) 접착 조성물의 수축으로 인한 파손이 적은 반도체 칩과 기판 사이의 전기적 접속을 갖는 반도체 소자 및 그 실장 방법
EP1465250A1 (en) Insulated power semiconductor module with reduced partial discharge and manufacturing method
US20020153598A1 (en) Device for attaching a semiconductor chip to a chip carrier
CN218388141U (zh) 具有经表面组装的电子构件的印刷电路板
JPH09293823A (ja) 半導体チップへのリード取付方法
JPH10256304A (ja) 半導体装置の製造方法
JPH02285650A (ja) 半導体装置及びその製造方法
JPH11135568A (ja) 半導体装置及びその製造方法
JPH03209840A (ja) 半導体装置の製造方法
JPH04171970A (ja) 半導体装置
JPS62132331A (ja) 半導体装置の製造方法
JPH0425142A (ja) 半導体素子の実装方法
JPH0274092A (ja) 実装体の製造方法
JPH0379063A (ja) 半導体装置及びその製造方法
JPS62281361A (ja) 半導体装置
JPH02101753A (ja) 半導体チップの取付構造

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20121114

Year of fee payment: 14

FPAY Annual fee payment

Payment date: 20131031

Year of fee payment: 15

FPAY Annual fee payment

Payment date: 20141103

Year of fee payment: 16

FPAY Annual fee payment

Payment date: 20151102

Year of fee payment: 17

EXPY Expiration of term