KR970063595A - 반도체 장치 및 그 제조방법 - Google Patents

반도체 장치 및 그 제조방법 Download PDF

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KR970063595A
KR970063595A KR1019960042934A KR19960042934A KR970063595A KR 970063595 A KR970063595 A KR 970063595A KR 1019960042934 A KR1019960042934 A KR 1019960042934A KR 19960042934 A KR19960042934 A KR 19960042934A KR 970063595 A KR970063595 A KR 970063595A
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electrode
chip
semiconductor device
substrate
tab tape
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KR1019960042934A
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KR100236885B1 (ko
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요미유끼 야마
마사오 고바야시
준 시바타
신지 바바
마사키 와타나베
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기다오까 다까시
미쓰비시 뎅끼 가부시끼가이샤
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Publication of KR970063595A publication Critical patent/KR970063595A/ko
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Abstract

[과제]
방열성이나 전기적 특성에 뛰어나며, 또한 다수의 전극을 가지는 집적회로에 적용할 수 있는 반도체 장치 및 그 제조방법을 구한다.
[해결수단]
반도체 칩(1)의 범프(2)를 가지는 면과 회로기판(3)의 랜드(5)를 가지는 면이 대면한 상태이다. 폴리이미드 테이프(6), TAB 리이드(lead)(7)은 TAB 테이프를 구성하고 있다. 펌프(2)와 랜드(5)는 평탄성이 유지된 TAB테이프를 통해서 전기적으로 접속한다. 따라서, 범프(2)로부터 (5)까지의 TAB리이드(7)의 배선길이가 짧게 끝나며, 그와 더불어로 TAB 리이드(7)에 흐르는 신호의 전기적 특성도 뛰어나다. 또, TAB 테이프를 사용함으로써 다수의 범프(2)를 가지는 반도체 칩(1)에 적용할 수가 있다.

Description

반도체 장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 실시의 형태1에 있어서의 반도체 장치를 표시한 도면.

Claims (19)

  1. 표면에 제1의 전극을 가지는 칩과, 표면에 제2의 전극을 가지는 기판과, 상기 제1의 전극과 상기 제2의 전극을 전기적으로 접속하는 TAB(Tape Automated Bonding)테이프를 구비하고, 상기 칩의 표면과 상기 기판의 표면이 마주보고 있으며, 사기 칩의 표면측으로부터 상기 기판의 표면측까지의 사이에만 상기 TAB 테이프가 존재하는 반도체 장치.
  2. 제1항에 있어서, 상기 칩에 접속되어, 방열성에 우수한 재질로 이루어지는 방열부를 더 구비한 반도체 장치.
  3. 제1항에 있어서, 상기 제2의 전극과 상기 TAB 테이프와의 접속점의 바로 아래를 제외하는 상기 기판의 이면에 상기 제2의 전극과 전기적으로 접속된 외부전극을 더 구비한 반도체 장치.
  4. 제1항에 있어서, 상기 TAB 테이프를 마이크로 스트립 선로로 하는 그라운드에 접속된 부재를 더 구비한 반도체 장치.
  5. 제1항에 있어서, 상기 기판에 형성되고, 상기 제2의 전극에 접속된 신호선과, 상기 제2의 전극, 상기 신호선을 마이크로 스트립 선로로 하는 그라운드에 접속된 부재를 더 구비한 반도체 장치.
  6. 제1항에 있어서, 상기 기판에 형성되고, 상기 제2의 전극에 접속된 신호선과, 상기 제2의 전극, 상기 신호선을 마이크로 스트립 선로로 하는 그라운드에 접속된 부재를 더 구비한 반도체 장치.
  7. 제4항에 있어서, 상기 부재는 상기 TAB 테이프에 포함되는 반도체 장치.
  8. 제4항에 있어서, 상기 부재는 상기 기판의 표면에 설정된 반도체 장치.
  9. 제1항에 있어서, 상기 기판에 형성되고 상기 제2의 전극에 접속된 신호선; 상기 제2의 전극과 상기 신호선을 마이크로 스트립 선로 또는 코프레이너 스트립 선로로 하는 접지에 접속된 부재를 더 구비하고, 상기 TAB와 상기 신호선과의 사이에 부재가 개재하는 반도체 장치.
  10. 제1항에 있어서, 상기 칩아래의 상기 기판의 표면에 설정되고, 상기 기판의 표면에서 파내려간 캐버티와, 상기 캐버티내에 설정된 제3의 전극과, 상기 칩의 표면에 설정된 제4의 전극을 더 구비하고, 상기 제3의 전극과 상기 제4의 전극을 전기적으로 접속한 반도체 장치.
  11. 제1항에 있어서, 상기 칩아래의 상기 기판의 표면에 설정된 제3의 전극과, 상기 칩의 표면에 설정된 제4의 전극과, 상기 제3의 전극과 상기 제4의 전극을 전기적으로 접속하는 도전성을 가지는 수지를 더 구비한 반도체 장치.
  12. 제1항에 있어서, 상기 칩아래의 상기 기판의 표면에 설정된 제3의 전극을 더 구비하고, 상기 TAB 테이프는 상기 제1의 전극과 상기 제3의 전극을 전기적으로 접속하는 반도체 장치.
  13. 제12항에 있어서, 상기 제1의 전극은 상기 칩의 내측에 형성된 전극과, 상기 칩의 외측에 형성된 전극을 포함하고, 상기 제2의 전극은 상기 칩아래의 위치이외의 상기 기판의 표면에 형성되고, 상기 칩의 외측에 형성된 전극과 상기 제2의 전극이 상기 TAB 테이프에 의해 전기적으로 접속되며, 상기 칩의 내측에 형성된 전극과 상기 제3의 전극이 상기 TAB 테이프에 의해 전기적으로 접속된 반도체 장치.
  14. 제1항에 있어서, 상기 칩 및 상기 TAB 테이프에만 접속하고, 상기 칩과 상기 TAB 테이프를 고정하기 위한 수지를 더 구비한 반도체 장치.
  15. 제1항에 있어서, 상기 칩아래의 상기 기판의 표면에서 이면으로의 관통구멍과, 상기 기판과 상기 칩과의 사이에 형성된 수지를 더 구비한 반도체 장치.
  16. 표면에서 이면으로 관통하는 관통구멍을 가지는 기판과, 상기 관통구멍내에 넣어둔 칩을 구비하고, 상기 반도체 장치를 시스템에 장치한 상태에서, 상기 반도체 장치를 장치하는 상기 시스템에 상기 칩이 접속하는 반도체 장치.
  17. 제16항에 있어서, 상기 시스템이 접촉하는 측의 상기 칩의 접촉면에, 적어도 상기 접촉면 중 가장 온도가 높은 장소에 열을 전도하는 재질로 된 부재를 더 구비하고, 상기 부재가 상기 시스템에 접속하는 반도체 장치.
  18. 전극을 가지는 칩을 준비하는 공정과, TAB 테이프를 준비하여, 상기 TAB 테이프에 상기 전극을 접속하는 공정과, 상기 칩과 상기 TAB 테이프와 접촉하는 수지를 형성하는 공정을 구비한 반도체 장치의 제조방법.
  19. 전극을 가지는 칩을 준비하는 공정과, 표면에서 이면으로 관통한 관통구멍을 가지는 기판을 준비하여, 상기 기판과 상기 칩과의 사이에 간극이 있는 상태로, 상기 기판과 상기 칩을 접속하는 공정과, 상기 관통구멍을 통해서, 상기 간극에 반도체 장치를 보호하는 수지를 외로부터 주입하는 공정을 구비한 반도체 장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960042934A 1996-02-01 1996-09-30 반도체 장치 및 그 제조방법 KR100236885B1 (ko)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100697240B1 (ko) * 2005-04-06 2007-03-22 에이유텍 주식회사 액정 디스플레이 패널 검사용 프루브핀의 제조방법

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5905300A (en) * 1994-03-31 1999-05-18 Vlsi Technology, Inc. Reinforced leadframe to substrate attachment
SG45122A1 (en) * 1995-10-28 1998-01-16 Inst Of Microelectronics Low cost and highly reliable chip-sized package
JP2980046B2 (ja) * 1997-02-03 1999-11-22 日本電気株式会社 半導体装置の実装構造および実装方法
US6465744B2 (en) * 1998-03-27 2002-10-15 Tessera, Inc. Graded metallic leads for connection to microelectronic elements
US5910686A (en) * 1998-07-23 1999-06-08 Vlsi Technology, Inc. Cavity down HBGA package structure
WO2000026959A1 (en) * 1998-10-30 2000-05-11 Seiko Epson Corporation Semiconductor device, method of manufacture thereof, circuit board and electronic device
CN1184684C (zh) * 2000-10-05 2005-01-12 三洋电机株式会社 半导体装置和半导体模块
US6507120B2 (en) * 2000-12-22 2003-01-14 Siliconware Precision Industries Co., Ltd. Flip chip type quad flat non-leaded package
TWI239087B (en) * 2004-07-23 2005-09-01 Siliconware Precision Industries Co Ltd Flip-chip semiconductor package with lead frame and method for fabricating the same
JP4875844B2 (ja) * 2004-11-25 2012-02-15 ローム株式会社 半導体装置の製造方法
US8481862B2 (en) * 2006-02-09 2013-07-09 General Dynamics Advanced Information Systems, Inc. Low profile compliant leads
US7851904B2 (en) * 2006-12-06 2010-12-14 Panasonic Corporation Semiconductor device, method for manufacturing the same, and semiconductor device mounting structure
US8742602B2 (en) * 2007-03-16 2014-06-03 Invensas Corporation Vertical electrical interconnect formed on support prior to die mount
US8723332B2 (en) * 2007-06-11 2014-05-13 Invensas Corporation Electrically interconnected stacked die assemblies
US8704379B2 (en) 2007-09-10 2014-04-22 Invensas Corporation Semiconductor die mount by conformal die coating
CN103325764B (zh) 2008-03-12 2016-09-07 伊文萨思公司 支撑安装的电互连管芯组件
US8350375B2 (en) * 2008-05-15 2013-01-08 Lsi Logic Corporation Flipchip bump patterns for efficient I-mesh power distribution schemes
US7863159B2 (en) * 2008-06-19 2011-01-04 Vertical Circuits, Inc. Semiconductor die separation method
US9153517B2 (en) 2008-05-20 2015-10-06 Invensas Corporation Electrical connector between die pad and z-interconnect for stacked die assemblies
US8841782B2 (en) * 2008-08-14 2014-09-23 Stats Chippac Ltd. Integrated circuit package system with mold gate
JP5963671B2 (ja) * 2009-06-26 2016-08-03 インヴェンサス・コーポレーション ジグザクの構成でスタックされたダイに関する電気的相互接続
TWI520213B (zh) 2009-10-27 2016-02-01 英維瑟斯公司 加成法製程之選擇性晶粒電絕緣
TWI544604B (zh) 2009-11-04 2016-08-01 英維瑟斯公司 具有降低應力電互連的堆疊晶粒總成
US8395241B2 (en) * 2009-11-25 2013-03-12 Intel Corporation Through silicon via guard ring
US9269676B2 (en) 2009-11-25 2016-02-23 Intel Corporation Through silicon via guard ring
US8415779B2 (en) * 2010-04-13 2013-04-09 Freescale Semiconductor, Inc. Lead frame for semiconductor package
US8803185B2 (en) * 2012-02-21 2014-08-12 Peiching Ling Light emitting diode package and method of fabricating the same
KR101641986B1 (ko) * 2012-08-01 2016-07-22 가부시키가이샤 무라타 세이사쿠쇼 전자 부품 및 전자 부품 모듈
JP5790633B2 (ja) * 2012-12-14 2015-10-07 株式会社村田製作所 キャリアテープ、包装用テープおよび電子部品連
EP3124169B1 (de) 2015-06-11 2020-04-01 Schneeberger Holding AG Positioniervorrichtung
US9490195B1 (en) 2015-07-17 2016-11-08 Invensas Corporation Wafer-level flipped die stacks with leadframes or metal foil interconnects
US9871019B2 (en) 2015-07-17 2018-01-16 Invensas Corporation Flipped die stack assemblies with leadframe interconnects
US9825002B2 (en) 2015-07-17 2017-11-21 Invensas Corporation Flipped die stack
US9508691B1 (en) 2015-12-16 2016-11-29 Invensas Corporation Flipped die stacks with multiple rows of leadframe interconnects
US10566310B2 (en) 2016-04-11 2020-02-18 Invensas Corporation Microelectronic packages having stacked die and wire bond interconnects
US9595511B1 (en) 2016-05-12 2017-03-14 Invensas Corporation Microelectronic packages and assemblies with improved flyby signaling operation
US9728524B1 (en) 2016-06-30 2017-08-08 Invensas Corporation Enhanced density assembly having microelectronic packages mounted at substantial angle to board
KR101694657B1 (ko) * 2016-08-04 2017-01-09 제엠제코(주) 방열 구조를 갖는 반도체 패키지
WO2018144494A1 (en) * 2017-01-31 2018-08-09 Crystal Is, Inc. Methods and packages for enhancing reliability of ultraviolet light-emitting devices
CN111524918A (zh) * 2019-02-01 2020-08-11 中芯集成电路(宁波)有限公司 摄像组件及其封装方法、镜头模组、电子设备
US20210249339A1 (en) * 2020-02-10 2021-08-12 Delta Electronics, Inc. Package structures
US11315857B2 (en) * 2020-02-10 2022-04-26 Delta Electronics, Inc. Package structures

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6482646A (en) * 1987-09-25 1989-03-28 Fujitsu Ltd Connection of integrated circuit element
JPH02252248A (ja) * 1989-03-27 1990-10-11 Nec Corp 半導体装置の製造方法
JPH0496240A (ja) * 1990-08-03 1992-03-27 Hitachi Ltd 半導体集積回路装置およびその実装方法
JPH07109867B2 (ja) * 1991-04-15 1995-11-22 インターナショナル・ビジネス・マシーンズ・コーポレイション 半導体チツプの冷却構造
US5350947A (en) * 1991-11-12 1994-09-27 Nec Corporation Film carrier semiconductor device
US5311059A (en) * 1992-01-24 1994-05-10 Motorola, Inc. Backplane grounding for flip-chip integrated circuit
US5249101A (en) * 1992-07-06 1993-09-28 International Business Machines Corporation Chip carrier with protective coating for circuitized surface
US5367435A (en) * 1993-11-16 1994-11-22 International Business Machines Corporation Electronic package structure and method of making same
US5608262A (en) * 1995-02-24 1997-03-04 Lucent Technologies Inc. Packaging multi-chip modules without wire-bond interconnection

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100697240B1 (ko) * 2005-04-06 2007-03-22 에이유텍 주식회사 액정 디스플레이 패널 검사용 프루브핀의 제조방법

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