KR970053677A - 히트싱크가 부착된 컬럼형 패키지 - Google Patents

히트싱크가 부착된 컬럼형 패키지 Download PDF

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KR970053677A
KR970053677A KR1019950067332A KR19950067332A KR970053677A KR 970053677 A KR970053677 A KR 970053677A KR 1019950067332 A KR1019950067332 A KR 1019950067332A KR 19950067332 A KR19950067332 A KR 19950067332A KR 970053677 A KR970053677 A KR 970053677A
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South Korea
Prior art keywords
heat sink
leads
package
semiconductor chip
type package
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KR1019950067332A
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English (en)
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KR100206880B1 (ko
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김선동
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문정환
Lg 반도체 주식회사
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Priority to KR1019950067332A priority Critical patent/KR100206880B1/ko
Priority to US08/749,963 priority patent/US5877561A/en
Priority to JP8342950A priority patent/JP2819282B2/ja
Priority to CN96114083A priority patent/CN1065659C/zh
Publication of KR970053677A publication Critical patent/KR970053677A/ko
Application granted granted Critical
Publication of KR100206880B1 publication Critical patent/KR100206880B1/ko
Priority to US09/412,646 priority patent/US6181560B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H01L21/4882—Assembly of heatsink parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

본 발명은 몸체의 상하면에 다수개의 리드와 히트싱크가 노출되도록 매설하여 외부의 충격으로부터 리드를 보호하고, 인쇄회로기판에 실장이 용이하고 또한 열방출효과를 높일 수 있도록 된 히트싱크가 부착된 컬럼형 패키지에 관한것으로, 그 구성은 소정두께로 그의 평면이 소정형상을 가진 몸체(11)와, 상기 몸체(11)의 상하면으로 노출되도록 매설된 다수개의 리드(12) 및 히트싱크(13)와, 다수개의 몬드패드가 그의 상면에 형성되어 있고, 상기 몸체(11)의 상면에 부착되는 반도체칩(15)과, 상기 몸체(11)의 리드(12)와 상기 반도체칩(15)의 다수개의 본드패드를 전기적으로 연결하는 금속와이어(14)와, 상기 반도체칩(15)과, 다수개의 리드(12)와, 금속와이어(14)를 포함하는 일정면적을 밀봉시키는 몰딩과정에 이용되는 에폭시몰딩컴파운드(epoxy molding compuond)로 구성된다.

Description

히트싱크가 부착된 컬럼형 패키지
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명에 따른 유니트 컬럼프레임과 컷팅된 몸체를 나타낸 사시도.

Claims (9)

  1. 소정두께로 그의 평면이 소정형상을 가진 몸체(11)와, 상기 몸체(11)의 상하면으로 노출되도록 매설된 다수개의 리드(12) 및 히트싱크(13)와, 다수개의 본드패드가 그의 상면에 형성되어있고, 상기 몸체(11)의 상면에 부착되는 반도체칩(15)과, 상기 몸체(11)의 리드(12)와 상기 반도체칩(15)의 다수개의 본드패드를 전기적으로 연결하는 금속와이어(14)와, 상기 반도체칩(15)과, 다수개의 리드(12)와, 금속와이어(14)를 포함하는 일정면적을 밀봉시키는 볼딩과정에 이용되는 에폭시몰딩컴파운드(epoxy molding compound)로 구성된 것을 특징으로 하는 히트싱크가 부착된 컬럼형 패키지.
  2. 제1항에 있어서, 상기 몸체(11)는 그의 상면에 단차(11a)가 형성된 것을 특징으로 하는 히트싱크가 부착된 컬럼형 패키지.
  3. 제1항에 있어서, 상기 몸체(11)는 절연성재질로 된 것을 특징으로 하는 히ㅐ트싱크가 부착된 컬럼형 패키지.
  4. 제1항에 있어서, 상기 몸체(11)에는 다수개의 반도체칩(11)이 안착될 수 있도록 된 것을 특징으로 하는 히트싱크가 부착된 컬럼형 패키지.
  5. 제1항에 있어서, 상기 몸체(11)는 그의 평면형상이 원형인 것을 특징으로 하는 히트싱크가 부착된 컬럼형 패키지.
  6. 제1항에 있어서, 상기 몸체(11)는 그의 평면형상이 사각형인 것을 특징으로 하는 히트싱크가 부착된 컬럼형 패키지.
  7. 제5항에 있어서, 상기 리드(12)는 상기 몸체(11)의 외측에 일측면애 노출되는 매설된 것을 특징으로 하는 히트싱크가 부착된 컬럼형 패키지.
  8. 제6항에 있어서, 상기 리드(12)는 상기 몸체(11)의 외측에 일측면이 노출되는 매설된 것을 특징으로 하는 히트싱크가 부착된 컬럼형 패키지.
  9. 소정두께로 그의 평면이 소정형상을 가지고 일정영역이 상방에서 하방으로 소정깊이를 가지고 홈(11a)가 형성된 몸체(11)와, 상기 몸체(11)의 상하면으로 노출되도록 매설된 다수개의 리드(12) 및 히트싱크(13)와, 다수개의 본드패드가 그의 상면에 형성되어있고, 상기 몸체(11)의 상면에 부착되는 반도체칩(15)과, 상기 몸체(11)의 리드(12)와 상기 반도체칩(15)의 다수개의 본드패드를 전기적으로 연결하는 금속와이어(14)와, 상기 몸체(11)의 상면은 커버(20)를 통해 밀봉되되, 상기 커버(20)는 상기 몸체(11)와 동일위치에 다수개의 리드(12) 및 히트싱크(13)가 노출되도록 매설되어 상기 몸체(11)와 전기적으로 연결된 것을 특징으로 하는 히트싱크가 부착된 컬럼형 패키지.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950067332A 1995-07-28 1995-12-29 히트싱크가 부착된 컬럼형 패키지 KR100206880B1 (ko)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1019950067332A KR100206880B1 (ko) 1995-12-29 1995-12-29 히트싱크가 부착된 컬럼형 패키지
US08/749,963 US5877561A (en) 1995-07-28 1996-11-18 Plate and column type semiconductor package having heat sink
JP8342950A JP2819282B2 (ja) 1995-12-29 1996-12-24 半導体パッケージおよびその製造方法
CN96114083A CN1065659C (zh) 1995-12-29 1996-12-26 具有热沉的平板型半导体封装
US09/412,646 US6181560B1 (en) 1995-07-28 1999-10-05 Semiconductor package substrate and semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950067332A KR100206880B1 (ko) 1995-12-29 1995-12-29 히트싱크가 부착된 컬럼형 패키지

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KR970053677A true KR970053677A (ko) 1997-07-31
KR100206880B1 KR100206880B1 (ko) 1999-07-01

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Publication number Priority date Publication date Assignee Title
MY135619A (en) 2002-11-12 2008-05-30 Nitto Denko Corp Epoxy resin composition for semiconductor encapsulation, and semiconductor device using the same
TWI233188B (en) 2003-10-07 2005-05-21 United Microelectronics Corp Quad flat no-lead package structure and manufacturing method thereof
CN100369241C (zh) * 2003-10-13 2008-02-13 联华电子股份有限公司 四方扁平无接脚型态的晶片封装结构及其工艺
CN102437824B (zh) * 2011-12-05 2015-03-11 北京大学 一种直冷式高集成度电荷灵敏前置放大器
CN105914191B (zh) * 2016-06-20 2018-03-16 深圳市宏钢机械设备有限公司 一种水冷散热的集成电路封装

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JP2612455B2 (ja) * 1987-09-30 1997-05-21 イビデン株式会社 半導体素子搭載用基板
IT1252136B (it) * 1991-11-29 1995-06-05 St Microelectronics Srl Struttura di dispositivo a semiconduttore con dissipatore metallico e corpo in plastica, con mezzi per una connessione elettrica al dissipatore di alta affidabilita'

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CN1065659C (zh) 2001-05-09
JP2819282B2 (ja) 1998-10-30
KR100206880B1 (ko) 1999-07-01
CN1156903A (zh) 1997-08-13
JPH09186273A (ja) 1997-07-15

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