CN1156903A - 具有热沉的平板型和柱型半导体封装 - Google Patents
具有热沉的平板型和柱型半导体封装 Download PDFInfo
- Publication number
- CN1156903A CN1156903A CN96114083A CN96114083A CN1156903A CN 1156903 A CN1156903 A CN 1156903A CN 96114083 A CN96114083 A CN 96114083A CN 96114083 A CN96114083 A CN 96114083A CN 1156903 A CN1156903 A CN 1156903A
- Authority
- CN
- China
- Prior art keywords
- encapsulation
- flat board
- parts
- lead
- heat sink
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 239000002184 metal Substances 0.000 claims abstract description 30
- 238000005538 encapsulation Methods 0.000 claims description 46
- 229920006336 epoxy molding compound Polymers 0.000 claims description 6
- 238000007789 sealing Methods 0.000 claims description 6
- 239000011810 insulating material Substances 0.000 claims description 5
- 238000004513 sizing Methods 0.000 claims description 2
- 238000005452 bending Methods 0.000 abstract description 4
- 238000009434 installation Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000007634 remodeling Methods 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- AOSZTAHDEDLTLQ-AZKQZHLXSA-N (1S,2S,4R,8S,9S,11S,12R,13S,19S)-6-[(3-chlorophenyl)methyl]-12,19-difluoro-11-hydroxy-8-(2-hydroxyacetyl)-9,13-dimethyl-6-azapentacyclo[10.8.0.02,9.04,8.013,18]icosa-14,17-dien-16-one Chemical compound C([C@@H]1C[C@H]2[C@H]3[C@]([C@]4(C=CC(=O)C=C4[C@@H](F)C3)C)(F)[C@@H](O)C[C@@]2([C@@]1(C1)C(=O)CO)C)N1CC1=CC=CC(Cl)=C1 AOSZTAHDEDLTLQ-AZKQZHLXSA-N 0.000 description 1
- 229940126657 Compound 17 Drugs 0.000 description 1
- 229940125898 compound 5 Drugs 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4882—Assembly of heatsink parts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
Claims (40)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950067332A KR100206880B1 (ko) | 1995-12-29 | 1995-12-29 | 히트싱크가 부착된 컬럼형 패키지 |
KR67332/1995 | 1995-12-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1156903A true CN1156903A (zh) | 1997-08-13 |
CN1065659C CN1065659C (zh) | 2001-05-09 |
Family
ID=19447659
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN96114083A Expired - Lifetime CN1065659C (zh) | 1995-12-29 | 1996-12-26 | 具有热沉的平板型半导体封装 |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP2819282B2 (zh) |
KR (1) | KR100206880B1 (zh) |
CN (1) | CN1065659C (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7291908B2 (en) | 2003-10-07 | 2007-11-06 | United Microelectronics Corp. | Quad flat no-lead package structure and manufacturing method thereof |
CN100369241C (zh) * | 2003-10-13 | 2008-02-13 | 联华电子股份有限公司 | 四方扁平无接脚型态的晶片封装结构及其工艺 |
CN102437824A (zh) * | 2011-12-05 | 2012-05-02 | 北京大学 | 一种直冷式高集成度电荷灵敏前置放大器 |
CN105914191B (zh) * | 2016-06-20 | 2018-03-16 | 深圳市宏钢机械设备有限公司 | 一种水冷散热的集成电路封装 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE60314218T2 (de) | 2002-11-12 | 2007-09-27 | Nitto Denko Corp., Ibaraki | Gefüllte Epoxidharz-Zusammensetzung zur Einkapselung von Halbleitern sowie ein damit eingekapselter Halbleiterbauteil |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2612455B2 (ja) * | 1987-09-30 | 1997-05-21 | イビデン株式会社 | 半導体素子搭載用基板 |
IT1252136B (it) * | 1991-11-29 | 1995-06-05 | St Microelectronics Srl | Struttura di dispositivo a semiconduttore con dissipatore metallico e corpo in plastica, con mezzi per una connessione elettrica al dissipatore di alta affidabilita' |
-
1995
- 1995-12-29 KR KR1019950067332A patent/KR100206880B1/ko not_active IP Right Cessation
-
1996
- 1996-12-24 JP JP8342950A patent/JP2819282B2/ja not_active Expired - Fee Related
- 1996-12-26 CN CN96114083A patent/CN1065659C/zh not_active Expired - Lifetime
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7291908B2 (en) | 2003-10-07 | 2007-11-06 | United Microelectronics Corp. | Quad flat no-lead package structure and manufacturing method thereof |
CN100369241C (zh) * | 2003-10-13 | 2008-02-13 | 联华电子股份有限公司 | 四方扁平无接脚型态的晶片封装结构及其工艺 |
CN102437824A (zh) * | 2011-12-05 | 2012-05-02 | 北京大学 | 一种直冷式高集成度电荷灵敏前置放大器 |
CN105914191B (zh) * | 2016-06-20 | 2018-03-16 | 深圳市宏钢机械设备有限公司 | 一种水冷散热的集成电路封装 |
Also Published As
Publication number | Publication date |
---|---|
CN1065659C (zh) | 2001-05-09 |
KR100206880B1 (ko) | 1999-07-01 |
JP2819282B2 (ja) | 1998-10-30 |
KR970053677A (ko) | 1997-07-31 |
JPH09186273A (ja) | 1997-07-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C06 | Publication | ||
PB01 | Publication | ||
C14 | Grant of patent or utility model | ||
FG4A | Grant of patent | ||
GR01 | Patent grant | ||
C56 | Change in the name or address of the patentee |
Owner name: HYNIX SEMICONDUCTOR INC. Free format text: FORMER NAME OR ADDRESS: LG SEMICON CO., LTD. |
|
CP03 | Change of name, title or address |
Address after: North Chungcheong Province Patentee after: Hairyoksa Semiconductor Co., Ltd. Address before: North Chungcheong Province Patentee before: LG Semicon Co., Ltd. |
|
ASS | Succession or assignment of patent right |
Owner name: MAGNACHIP CO., LTD. Free format text: FORMER OWNER: HYNIX SEMICONDUCTOR INC. Effective date: 20070601 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20070601 Address after: North Chungcheong Province Patentee after: Magnachip Semiconductor Ltd. Address before: North Chungcheong Province Patentee before: Hairyoksa Semiconductor Co., Ltd. |
|
CX01 | Expiry of patent term |
Granted publication date: 20010509 |
|
EXPY | Termination of patent right or utility model |