KR970052830A - 반도체 소자의 제조방법 - Google Patents

반도체 소자의 제조방법 Download PDF

Info

Publication number
KR970052830A
KR970052830A KR1019950055136A KR19950055136A KR970052830A KR 970052830 A KR970052830 A KR 970052830A KR 1019950055136 A KR1019950055136 A KR 1019950055136A KR 19950055136 A KR19950055136 A KR 19950055136A KR 970052830 A KR970052830 A KR 970052830A
Authority
KR
South Korea
Prior art keywords
metal wiring
interlayer insulating
insulating film
silicon oxide
oxide film
Prior art date
Application number
KR1019950055136A
Other languages
English (en)
Other versions
KR100199348B1 (ko
Inventor
신동선
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950055136A priority Critical patent/KR100199348B1/ko
Priority to US08/771,571 priority patent/US5744397A/en
Publication of KR970052830A publication Critical patent/KR970052830A/ko
Application granted granted Critical
Publication of KR100199348B1 publication Critical patent/KR100199348B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/972—Stored charge erasure

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

본 발명은 다중 금속배선을 사용하는 고집적 반도체 소자에서 하층 금속 배선을 형성한 후, 금속층간 절연막의 표면 평탄화를 실현하기 위해 사용되는 O3-TEOS 실리콘 산화막을 중착하기 전에 실리콘 기판을 접지시킨 상태에서 하층 금속배선에 전자빔을 조사시켜 실리콘 기판과 접속되지 않은 하층 금속배선의 양전하 상태를 전기적으로 중성화시킨다.
따라서, 본 발명은 양전하가 대전된 하층 금속배선을 전기적으로 중성화시키므로 균일한 두께의 O3-TEOS 실리콘 산화막을 형성할 수 있으며, 이로 인하여 O3-TEOS 실리콘 산화막상에 형성되는 상층 금속배선이 균일한 두께로 형성되어 상층 금속 배선의 단선 또는 선이 가늘게 되는 현상을 방지할 수 있어 소자의 신뢰성을 향상시킬 뿐만 아니라, 보다 가는 선폭이 요구되는 초고집적 소자의 실현을 가능하게 한다.
* 선택도 :제2C 및 3C도.

Description

반도체 소자의 제조방법.
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2A 내지 2C도는 본 발명의 제1실시예에 의한 반도체 소자의 제조방법을 설명하기 위해 도시한 소자의 단면도.

Claims (5)

  1. 반도체 소자의 제조방법에 있어서, 금속배선을 형성한 후, 금속층간 절연막의 평탄화막으로 O3-TEOS 실리콘 산화막을 형성하기 전에 상기 금속배선 내의 전하 분포를 전기적으로 중성화시키는 것을 포함하는 반도체소자의 제조방법.
  2. 반도체소자의 제조방법에 있어서, 층간 절연막상에 금속배선이 형성된 실리콘 기판에 제공되는 단계; 전자빔을 조사하여 상기 금속 배선 내의 전하 분포를 전기적으로 중성화시키는 단계; 및 상기 금속배선을 포함한 상기 층간 절연막상에 제1금속층간 절연막을 형성한 후, 상기 제1금속층간 절연막상에 O3-TEOS 실리콘 산화막을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체소자의 제조방법.
  3. 제2항에 있어서, 상기 전자빔은 상기 실리콘 기판에 접지된 상태에서 조사되는 것을 특징으로 하는 반도체소자의 제조방법.
  4. 반도체소자의 제조방법에 있어서, 층간 절연막상에 금속배선이 형성된 실리콘 기판에 제공되는 단계; 상기 금속배선을 포함한 상기 층간 절연막상에 제1금속층간 절연막을 형성하는 단계; 전자빔을 조사하여 상기 금속 배선 내의 전하 분포를 전기적으로 중성화시키는 단계; 및 상기 제1금속층간 절연막상에 O3-TEOS 실리콘 산화막을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체소자의 제조방법.
  5. 제4항에 있어서, 상기 전자빔은 상기 실리콘 기판에 접지된 상태에서 조사되는 것을 특징으로 하는 반도체소자의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950055136A 1995-12-23 1995-12-23 반도체 소자의 제조방법 KR100199348B1 (ko)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019950055136A KR100199348B1 (ko) 1995-12-23 1995-12-23 반도체 소자의 제조방법
US08/771,571 US5744397A (en) 1995-12-23 1996-12-20 Method of planarizing an insulating layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950055136A KR100199348B1 (ko) 1995-12-23 1995-12-23 반도체 소자의 제조방법

Publications (2)

Publication Number Publication Date
KR970052830A true KR970052830A (ko) 1997-07-29
KR100199348B1 KR100199348B1 (ko) 1999-06-15

Family

ID=19443603

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950055136A KR100199348B1 (ko) 1995-12-23 1995-12-23 반도체 소자의 제조방법

Country Status (2)

Country Link
US (1) US5744397A (ko)
KR (1) KR100199348B1 (ko)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3819604B2 (ja) * 1998-08-31 2006-09-13 株式会社東芝 成膜方法
JP3631463B2 (ja) * 2001-12-27 2005-03-23 株式会社東芝 不揮発性半導体記憶装置
US6753260B1 (en) * 2001-10-05 2004-06-22 Taiwan Semiconductor Manufacturing Company Composite etching stop in semiconductor process integration
JP4458129B2 (ja) * 2007-08-09 2010-04-28 ソニー株式会社 半導体装置およびその製造方法
US8296498B2 (en) * 2007-11-13 2012-10-23 Sandisk Technologies Inc. Method and system for virtual fast access non-volatile RAM

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4116721A (en) * 1977-11-25 1978-09-26 International Business Machines Corporation Gate charge neutralization for insulated gate field-effect transistors
US5286978A (en) * 1989-10-25 1994-02-15 Kabushiki Kaisha Toshiba Method of removing electric charge accumulated on a semiconductor substrate in ion implantation
JPH04120732A (ja) * 1990-09-12 1992-04-21 Hitachi Ltd 固体素子及びその製造方法
US5254497A (en) * 1992-07-06 1993-10-19 Taiwan Semiconductor Manufacturing Company Method of eliminating degradation of a multilayer metallurgy/insulator structure of a VLSI integrated circuit
KR970007116B1 (ko) * 1993-08-31 1997-05-02 삼성전자 주식회사 반도체장치의 절연층 형성방법 및 그 형성장치

Also Published As

Publication number Publication date
US5744397A (en) 1998-04-28
KR100199348B1 (ko) 1999-06-15

Similar Documents

Publication Publication Date Title
US4735679A (en) Method of improving silicon-on-insulator uniformity
US6531783B1 (en) Method of via formation for multilevel interconnect integrated circuits
JPH08501904A (ja) 通気性エッチ停止層を有するチップ相互接続部
KR20010082057A (ko) 반도체장치 및 그 제조방법
KR970052830A (ko) 반도체 소자의 제조방법
US6677231B1 (en) Method for increasing adhesion ability of dielectric material in semiconductor
US20030064553A1 (en) Method of producing semiconductor device and its structure
KR980005436A (ko) 돌출형 텅스텐-플러그를 구비한 배선막 구조 및 그 제조방법
KR20010004008A (ko) 에어-갭을 갖는 반도체 소자의 금속배선 형성방법
KR970053546A (ko) 반도체 장치의 금속 배선 형성 방법
KR960039148A (ko) 반도체 장치의 층간접속방법
TW375782B (en) Method of forming intermediate insulation layer in semiconductor device
KR100973261B1 (ko) 반도체소자의 텅스텐 플러그 형성 방법
KR960002644A (ko) 반도체 소자의 층간 절연막 형성방법
KR980005474A (ko) 반도체 소자 제조방법
KR970052364A (ko) 반도체 장치의 콘택 형성 방법
KR970052943A (ko) 반도체 소자의 금속 배선 형성방법
KR980005440A (ko) 반도체 장치의 제조방법
KR960002648A (ko) 반도체 소자의 금속층간 절연막 형성방법
KR980005828A (ko) 반도체 소자의 평탄화 방법
KR970052386A (ko) 반도체 장치의 금속 배선 형성 방법
KR960002576A (ko) 반도체소자의 금속배선 형성방법
KR960035812A (ko) 미세 접촉창의 접촉방법
KR970052864A (ko) 반도체소자의 층간절연막 형성방법
KR980005624A (ko) 반도체 소자의 금속배선 형성방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20070221

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee