KR970052527A - Mos구조용 게이트 전극 제조 방법 - Google Patents

Mos구조용 게이트 전극 제조 방법 Download PDF

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KR970052527A
KR970052527A KR1019960067909A KR19960067909A KR970052527A KR 970052527 A KR970052527 A KR 970052527A KR 1019960067909 A KR1019960067909 A KR 1019960067909A KR 19960067909 A KR19960067909 A KR 19960067909A KR 970052527 A KR970052527 A KR 970052527A
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South Korea
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layer
electrode
gate electrode
forming
spacer
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KR1019960067909A
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KR100395667B1 (ko
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베른하르트 루스티히
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로더리히 네테부쉬;롤프 옴케
지멘스 악티엔게젤샤프트
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Publication of KR970052527A publication Critical patent/KR970052527A/ko
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Publication of KR100395667B1 publication Critical patent/KR100395667B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28132—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
  • Static Random-Access Memory (AREA)

Abstract

MOS구조용 게이트 전극, 특히 단-채널 MOS트랜지스터를 제조하기 위하여, 하드마스크(8)는 에칭 마스크로서 게이트 전극의 재료인 스페이서(7)를 이용하여 형성되고, 또한 하드마스크는 게이트 전극을 구성하는데 이용된다. 이러한 방법은 특히 100nm이하의 채널길이를 가진 매우 얇은 게이트 전극을 가진 게이트 전극을 제조하는데 특히 적합하다.

Description

MOS구조용 게이트 전극 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 등각 단부 영역을 갖는 층을 증착한 후의 반도체 기판 도면.
제4도는 스페이서를 형성한 후의 반도체 기판 도면.
제5도는 하드 마스크를 형성한 후의 반도체 기판 도면.

Claims (3)

  1. MOS구조용 게이트 전극을 제조하는 방법에 있어서,-게이트 유전체(2)를 가진 반도체 기판(1)에 전극층(3)을 제공하는 단계; -상기 전극층(3)에 보조층(4)을 제공하는 단계; -보조층(4)에 스탭을 형성하고, 스탭형 구조의 보조층(4)으로 상기 전극층(3)의 표면을 덮는 단계; -상기 전극층(3)의 재료로부터 스탭에 스페이서(7)를 형성하는 단계; -에칭 마스크로서 상기 스페이서(7)를 이용하는 이방성 에칭에 의해 스탭형 구조의 상기 보조층(4)으로부터 하드 마스크(8)를 형성하는 단계; -에칭 마스크로서 상기 하드 마스크를 이용하는 상기 전극층(3)의 이방성 에칭에 의해 상기 게이트 전극(9)을 형성하는 단계; 및 -2개의 재료층만을 이용하여 상기 보조층(4), 상기 스페이서(7), 상기 게이트 유전체(2)및 상기 전극층(3)을 형성하는 단계를 포함하는 것을 특징으로 하는 MOS구조용 게이트 전극 제조방법.
  2. 제1항에 있어서, 등각 단부 영역을 가진 층(6)의 증착 및 다음의 이방성 에칭에 의해 상기 스페이서(7)를 형성하는 것을 특징으로 하는 MOS구조용 게이트 전극 제조방법.
  3. 제1항 또는 제2항에 있어서, 상기 보조층(4)및 게이트 유전체(2)는 SiO2로 형성되고, 상기 전극층(3) 및 상기 스페이서는 폴리 실리콘으로 형성되는 것을 특징으로 하는 MOS구조용 게이트 전극 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960067909A 1995-12-21 1996-12-19 Mos구조용게이트전극제조방법 KR100395667B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19548056.2 1995-12-21
DE19548056A DE19548056C1 (de) 1995-12-21 1995-12-21 Verfahren zur Herstellung einer Gateelektrode für eine MOS-Struktur

Publications (2)

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KR970052527A true KR970052527A (ko) 1997-07-29
KR100395667B1 KR100395667B1 (ko) 2003-11-17

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Country Link
US (1) US5705414A (ko)
EP (1) EP0780888B1 (ko)
JP (1) JP3899152B2 (ko)
KR (1) KR100395667B1 (ko)
AT (1) ATE213094T1 (ko)
DE (2) DE19548056C1 (ko)
TW (2) TW383412B (ko)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5714039A (en) * 1995-10-04 1998-02-03 International Business Machines Corporation Method for making sub-lithographic images by etching the intersection of two spacers
DE19548058C2 (de) * 1995-12-21 1997-11-20 Siemens Ag Verfahren zur Herstellung eines MOS-Transistors
US5893735A (en) * 1996-02-22 1999-04-13 Siemens Aktiengesellschaft Three-dimensional device layout with sub-groundrule features
US5923981A (en) * 1996-12-31 1999-07-13 Intel Corporation Cascading transistor gate and method for fabricating the same
US6159861A (en) * 1997-08-28 2000-12-12 Nec Corporation Method of manufacturing semiconductor device
US6225201B1 (en) * 1998-03-09 2001-05-01 Advanced Micro Devices, Inc. Ultra short transistor channel length dictated by the width of a sidewall spacer
US6069044A (en) * 1998-03-30 2000-05-30 Texas Instruments-Acer Incorporated Process to fabricate ultra-short channel nMOSFETS with self-aligned silicide contact
US6261912B1 (en) * 1999-08-10 2001-07-17 United Microelectronics Corp. Method of fabricating a transistor
US6362057B1 (en) 1999-10-26 2002-03-26 Motorola, Inc. Method for forming a semiconductor device
US6630405B1 (en) 1999-12-20 2003-10-07 Chartered Semiconductor Manufacturing Ltd. Method of gate patterning for sub-0.1 μm technology
US6184116B1 (en) 2000-01-11 2001-02-06 Taiwan Semiconductor Manufacturing Company Method to fabricate the MOS gate
DE10030391C2 (de) * 2000-06-21 2003-10-02 Infineon Technologies Ag Verfahren zur Herstellung einer Anschlussfläche für vertikale sublithographische Halbleiterstrukturen
US6960806B2 (en) * 2001-06-21 2005-11-01 International Business Machines Corporation Double gated vertical transistor with different first and second gate materials
US6967351B2 (en) * 2001-12-04 2005-11-22 International Business Machines Corporation Finfet SRAM cell using low mobility plane for cell stability and method for forming
US6720231B2 (en) 2002-01-28 2004-04-13 International Business Machines Corporation Fin-type resistors
US6709982B1 (en) 2002-11-26 2004-03-23 Advanced Micro Devices, Inc. Double spacer FinFET formation
US6762448B1 (en) * 2003-04-03 2004-07-13 Advanced Micro Devices, Inc. FinFET device with multiple fin structures
US6716686B1 (en) 2003-07-08 2004-04-06 Advanced Micro Devices, Inc. Method for forming channels in a finfet device
US7498225B1 (en) 2003-12-04 2009-03-03 Advanced Micro Devices, Inc. Systems and methods for forming multiple fin structures using metal-induced-crystallization
US7521371B2 (en) * 2006-08-21 2009-04-21 Micron Technology, Inc. Methods of forming semiconductor constructions having lines
US7670914B2 (en) * 2006-09-28 2010-03-02 Globalfoundries Inc. Methods for fabricating multiple finger transistors
CN101536153B (zh) * 2006-11-06 2011-07-20 Nxp股份有限公司 制造fet栅极的方法
US7772048B2 (en) * 2007-02-23 2010-08-10 Freescale Semiconductor, Inc. Forming semiconductor fins using a sacrificial fin
US11942133B2 (en) * 2021-09-02 2024-03-26 Kepler Computing Inc. Pedestal-based pocket integration process for embedded memory

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4358340A (en) * 1980-07-14 1982-11-09 Texas Instruments Incorporated Submicron patterning without using submicron lithographic technique
JP2699179B2 (ja) * 1988-09-20 1998-01-19 株式会社サクラクレパス 筆記用水性インキ組成物
USH986H (en) * 1989-06-09 1991-11-05 International Business Machines Corporation Field effect-transistor with asymmetrical structure
US5202272A (en) * 1991-03-25 1993-04-13 International Business Machines Corporation Field effect transistor formed with deep-submicron gate

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JP3899152B2 (ja) 2007-03-28
TW334567B (en) 1998-06-21
DE19548056C1 (de) 1997-03-06
TW383412B (en) 2000-03-01
ATE213094T1 (de) 2002-02-15
KR100395667B1 (ko) 2003-11-17
US5705414A (en) 1998-01-06
DE59608704D1 (de) 2002-03-21
EP0780888B1 (de) 2002-02-06
EP0780888A2 (de) 1997-06-25
JPH09181303A (ja) 1997-07-11
EP0780888A3 (de) 1997-07-16

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