KR970051385A - 플래쉬 메모리셀의 문턱전압 조정회로 - Google Patents

플래쉬 메모리셀의 문턱전압 조정회로 Download PDF

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Publication number
KR970051385A
KR970051385A KR1019950052513A KR19950052513A KR970051385A KR 970051385 A KR970051385 A KR 970051385A KR 1019950052513 A KR1019950052513 A KR 1019950052513A KR 19950052513 A KR19950052513 A KR 19950052513A KR 970051385 A KR970051385 A KR 970051385A
Authority
KR
South Korea
Prior art keywords
memory cell
output
threshold voltage
voltage
flash memory
Prior art date
Application number
KR1019950052513A
Other languages
English (en)
Other versions
KR100217917B1 (ko
Inventor
홍순원
손재현
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950052513A priority Critical patent/KR100217917B1/ko
Priority to GB9626400A priority patent/GB2308478B/en
Priority to US08/769,507 priority patent/US5721705A/en
Priority to JP34079096A priority patent/JP2857618B2/ja
Publication of KR970051385A publication Critical patent/KR970051385A/ko
Application granted granted Critical
Publication of KR100217917B1 publication Critical patent/KR100217917B1/ko

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G11C16/3486—Circuits or methods to prevent overprogramming of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing

Landscapes

  • Read Only Memory (AREA)

Abstract

본 발명은 플레쉬 메모리셀의 문턱전압(VT)을 정밀하게 조정할 수 있도록 한 플레쉬 메모리셀의 문턱전압조정회로에 관한 것이다.

Description

플래쉬 메모리셀의 문턱전압 조정회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명에 따른 플래쉬 메모리셀의 문턱전압 조정회로도.

Claims (3)

  1. 프로그램 전압 공급에 의해 프로그램 되는 메모리셀과, 전원전압을 어느 한 단자로 입력으로 하며 상기 메모리셀의 프로그램 상태에 따라 상기 메모리셀로 흐르는 전류에 의해 출력 전압이 제어되는 오피앰프와, 상기 오피앰프의 출력 및 기준전압의 입력에 따라 제어되는 비교기와, 상기 비교기의 출력을 입력으로하여 프로그램 전압을 공급하기 위한 트랜스미션 게이트로 구성되는 것을 특징으로 하는 플래쉬 메모리셀의 문턱전압 조정회로.
  2. 제1항에 있어서, 상기 오피앰프는 그 출력이 기준저항 값에 따라 조정이 가능하도록 구성되는 것을 특징으로 하는 플래쉬 메모리셀을 문턱전압 조정회로.
  3. 제1항에 있어서, 상기 비교기는 그 출력이 기준전압의 값에 따라 조정이 가능하도록 구성되는 것을 특징으로 하는 플래쉬 메모리셀의 문턱전압 조정회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950052513A 1995-12-20 1995-12-20 플래쉬 메모리셀의 문턱전압 조정회로 KR100217917B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019950052513A KR100217917B1 (ko) 1995-12-20 1995-12-20 플래쉬 메모리셀의 문턱전압 조정회로
GB9626400A GB2308478B (en) 1995-12-20 1996-12-19 Circuit for controlling a threshold voltage in a flash memory cell
US08/769,507 US5721705A (en) 1995-12-20 1996-12-19 Circuitry for controlling a threshold voltage in a flash memory cell
JP34079096A JP2857618B2 (ja) 1995-12-20 1996-12-20 フラッシュメモリセルの閾値電圧調整回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950052513A KR100217917B1 (ko) 1995-12-20 1995-12-20 플래쉬 메모리셀의 문턱전압 조정회로

Publications (2)

Publication Number Publication Date
KR970051385A true KR970051385A (ko) 1997-07-29
KR100217917B1 KR100217917B1 (ko) 1999-09-01

Family

ID=19441723

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950052513A KR100217917B1 (ko) 1995-12-20 1995-12-20 플래쉬 메모리셀의 문턱전압 조정회로

Country Status (4)

Country Link
US (1) US5721705A (ko)
JP (1) JP2857618B2 (ko)
KR (1) KR100217917B1 (ko)
GB (1) GB2308478B (ko)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6133853A (en) 1998-07-30 2000-10-17 American Calcar, Inc. Personal communication and positioning system
JP4663094B2 (ja) * 2000-10-13 2011-03-30 株式会社半導体エネルギー研究所 半導体装置
JP4907011B2 (ja) * 2001-04-27 2012-03-28 株式会社半導体エネルギー研究所 不揮発性メモリとその駆動方法、及び半導体装置
KR100469375B1 (ko) * 2002-03-13 2005-02-02 매그나칩 반도체 유한회사 플래쉬 메모리 소자
WO2007015358A1 (ja) * 2005-08-02 2007-02-08 Nec Corporation 磁気ランダムアクセスメモリ及びその動作方法
US9747157B2 (en) 2013-11-08 2017-08-29 Sandisk Technologies Llc Method and system for improving error correction in data storage
US10755779B2 (en) * 2017-09-11 2020-08-25 Silicon Storage Technology, Inc. Architectures and layouts for an array of resistive random access memory cells and read and write methods thereof

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2828855C2 (de) * 1978-06-30 1982-11-18 Siemens AG, 1000 Berlin und 8000 München Wortweise elektrisch umprogrammierbarer, nichtflüchtiger Speicher sowie Verfahren zum Löschen bzw. Einschreiben eines bzw. in einen solchen Speicher(s)
US4797856A (en) * 1987-04-16 1989-01-10 Intel Corporation Self-limiting erase scheme for EEPROM
US4888738A (en) * 1988-06-29 1989-12-19 Seeq Technology Current-regulated, voltage-regulated erase circuit for EEPROM memory
EP0463378B1 (en) * 1990-06-29 1997-03-05 Texas Instruments Incorporated An electrically-erasable, electrically-programmable read-only memory cell with a selectable threshold voltage and methods for its use
US5200919A (en) * 1990-06-29 1993-04-06 Texas Instruments Incorporated Electrically-erasable, electrically-programmable read-only memory cell with a selectable threshold voltage and methods for its use
US5396468A (en) * 1991-03-15 1995-03-07 Sundisk Corporation Streamlined write operation for EEPROM system
JPH05135595A (ja) * 1991-11-14 1993-06-01 Fujitsu Ltd 不揮発性半導体記憶装置
US5428578A (en) * 1993-08-12 1995-06-27 Texas Instruments Incorporated Biasing circuit and method to achieve compaction and self-limiting erase in flash EEPROMs
US5359558A (en) * 1993-08-23 1994-10-25 Advanced Micro Devices, Inc. Flash eeprom array with improved high endurance
US5467306A (en) * 1993-10-04 1995-11-14 Texas Instruments Incorporated Method of using source bias to increase threshold voltages and/or to correct for over-erasure of flash eproms
JPH08273381A (ja) * 1995-03-27 1996-10-18 Sanyo Electric Co Ltd 不揮発性メモリの消去特性向上回路
KR0172831B1 (ko) * 1995-09-18 1999-03-30 문정환 비휘발성 메모리를 프로그램하는 방법

Also Published As

Publication number Publication date
GB2308478A (en) 1997-06-25
GB2308478B (en) 2000-01-26
JP2857618B2 (ja) 1999-02-17
GB9626400D0 (en) 1997-02-05
KR100217917B1 (ko) 1999-09-01
US5721705A (en) 1998-02-24
JPH09185893A (ja) 1997-07-15

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