KR970024167A - 반도체장치의 트윈웰 제조방법 - Google Patents

반도체장치의 트윈웰 제조방법 Download PDF

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KR970024167A
KR970024167A KR1019950034564A KR19950034564A KR970024167A KR 970024167 A KR970024167 A KR 970024167A KR 1019950034564 A KR1019950034564 A KR 1019950034564A KR 19950034564 A KR19950034564 A KR 19950034564A KR 970024167 A KR970024167 A KR 970024167A
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well
silicon nitride
resultant
oxide film
forming
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KR1019950034564A
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KR0155894B1 (ko
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김봉석
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

포토어라인이 가능한 최소수준까지 웰단차를 축소할 수 있는 트윈웰 제조방법이 포함되어 있다. 본 발명은 실리콘기판 전면에 제1산화막, 실리콘질화막 형성공정, 상기 결과물 전면에 제1불순물이온 주입공정, 사진/식각 공정에 의한 실리콘질화막 패턴 형성공정, 상기 결과물 전면에 제2불순물 이온 주입공정, 상기 결과물 전면에 제2산화막을 형성하고 웰확산을 하는 공정, 상기 실리콘질화막 패턴, 상기 제1산화막, 상기 제2산화막의 제거공정을 포함하는 것을 특징으로 한다. 본 발명의 트윈웰 제조방법은 웰단차를 포토얼라인(Photo Align)이 가능한 최소수준까지 조절할 수 있고, 제2산화막의 두께가 얇기 때문에 산화 시간이 짧고, 웰단차가 정도로 작으므로 후속공정에서 특히 게이트 패터닝시 균일한 크기의 패터닝이 가능하다.

Description

반도체장치의 트윈웰 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제11도 내지 제15도는 본 발명의 제1실시예에 의한 반도체장치의 트윈웰 제조방법을 나타내는 도면이다.

Claims (4)

  1. 반도체장치의 트윈웰(Twin-well) 제조방법에 있어서, 실리콘기판의 전면에 제1산화막 및 실리콘질화막을 순차적으로 형성하는 공정; 상기 결과물의 전면에 제1웰 형성을 위하여 제1불순물이온을 주입하는 공정; 상기 결과물의 전면에 포토레지스트 패턴을 형성하는 공정; 상기 포토레지스트 패턴이 없는 쪽의 상기 실리콘질화막을 식각하여 실리콘질화막 패턴을 형성하는 공정; 상기 결과물의 전면에 제2웰 형성을 위하여 제2불순물 이온을 주입하는 공정; 상기 포토레지스트 패턴을 제거하는 공정; 상기 결과물의 전면에 제2산화막을 형성하고 웰확산을 하는 공정; 상기 실리콘질화막 패턴을 먼저 제거하고 상기 제1산화막 및 상기 제2산화막을 제거하는 공정을 포함하는 것을 특징으로 하는 반도체장치의 트윈웰 제조방법.
  2. 제1항에 있어서, 상기 제1산화막 및 상기 실리콘질화막의 두께를 각각 100Å 내지 1000Å로 하는 것을 특징으로 하는 반도체장치의 트윈웰 제조방법.
  3. 제1항에 있어서, 상기 제2산화막의 두께를 400Å 내지 1000Å로 하는 것을 특징으로 하는 반도체장치의 트윈웰 제조방법.
  4. 반도체장치의 트윈웰(Twin-well) 제조방법에 있어서, 실리콘기판의 전면에 제1산화막을 형성하는 공정; 상기 결과물의 전면에 제1웰 형성을 위하여 제1불순물이온을 주입하는 공정; 상기 결과물의 전면에 실리콘질화막을 형성하는 공정; 상기 결과물의 전면에 포토레지스트 패턴을 형성하는 공정; 상기 포토레지스트 패턴이 없는 쪽의 상기 실리콘질화막을 식각하여 실리콘질화막 패턴을 형성하는 공정; 상기 결과물의 전면에 제2웰 형성을 위한 제2불순물 이온을 주입하는 공정; 상기 포토레지스트 패턴을 제거하는 공정; 상기 결과물의 전면에 제2산화막을 형성하고 웰확산을 하는 공정; 상기 실리콘질화막 패턴을 먼저 제거하고 상기 제1산화막 및 제2산화막을 제거하는 공정을 포함하는 것을 특징으로 하는 반도체장치의 트윈웰 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950034564A 1995-10-09 1995-10-09 반도체장치의 트윈웰 제조방법 KR0155894B1 (ko)

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KR1019950034564A KR0155894B1 (ko) 1995-10-09 1995-10-09 반도체장치의 트윈웰 제조방법

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KR1019950034564A KR0155894B1 (ko) 1995-10-09 1995-10-09 반도체장치의 트윈웰 제조방법

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KR970024167A true KR970024167A (ko) 1997-05-30
KR0155894B1 KR0155894B1 (ko) 1998-10-15

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