KR970024139A - 캐패시터의 전하저장 전극 형성 방법 - Google Patents

캐패시터의 전하저장 전극 형성 방법 Download PDF

Info

Publication number
KR970024139A
KR970024139A KR1019950034844A KR19950034844A KR970024139A KR 970024139 A KR970024139 A KR 970024139A KR 1019950034844 A KR1019950034844 A KR 1019950034844A KR 19950034844 A KR19950034844 A KR 19950034844A KR 970024139 A KR970024139 A KR 970024139A
Authority
KR
South Korea
Prior art keywords
polysilicon
charge storage
forming
storage electrode
oxide film
Prior art date
Application number
KR1019950034844A
Other languages
English (en)
Inventor
권오성
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950034844A priority Critical patent/KR970024139A/ko
Publication of KR970024139A publication Critical patent/KR970024139A/ko

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야
반도체 소자 제조 방법.
2. 발명이 해결하려고 하는 기술적 과제
종래의 전하저장 전극은 공정이 길고 복잡하며 제조기술이 어려워 불량을 많이 일으키고 구조적으로도 불안정하고 또한 충분한 용량도 가지기 어렵다는 문제점을 해결하고자 함.
3. 발명의 해결방법의 요지
두 번의 마스크 패턴을 적절히 형성하여 이용하여 보다 견고하고 고용량을 수용할 수 있는 터널 형태를 형성한 캐패시터의 전하저장 전극을 제조하고자 함.
4. 발명의 중요한 용도
반도체 소자의 캐패시터의 전하저장 전극을 형성하는데 이용됨.

Description

캐패시터의 전하저장 전극 형성 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1A도 내지 제1C도는 본 발명의 반도체 소자의 캐패시터의 전하저장 전극 형성 방법에 따른 공정도.
제2도는 본 발명의 제 1 및 제 2 포토레지스트 패턴을 표시한 평면도.

Claims (5)

  1. 반도체 소자의 캐패시터의 전하저장 전극을 제조하는 방법에 있어서, 반도체 기판에 소자 분리막 및 모스트랜지스터가 형성된 구조 상에 평탄화된 층간절연막을 형성하고 열산화막을 형성하는 단계와, 전하저장 전극을 형성하기 위한 콘택홀을 형성하고 전하저장 전극용 제 1 폴리실리콘을 증착하는 단게와, 저압-화학증착법으로 산화막을 형성하는 단계와, 형성될 터널 모양의 전하저장 전극의 터널의 폭을 정의 하기 위한 제 1 포토레지스트 패턴을 형성하고 상기 제 1 포토레지스트 패턴을 식각 베리어로 이용하여 산화막과 상기 제 1 폴리실리콘층을 식각하는 단계와, 잔류 포토레지스트를 제거하고 제 2 폴리실리콘을 증착하는 단계와, 상기 제 2 폴리실리콘과 상기 산화막 및 상기 제 1 폴리실리콘이 차례로 적재된 영역보다 양옆으로 소정의 폭만큼 큰 직사각형의 제 2 포토레지스트 패턴을 형성하는 단계와, 상기 2 포토레지스트 패턴을 식각 베리어로 이용하여 상기 제 2 폴리실리콘층을 건식식각 하는 단계와, 상기 산화막을 습식식각하는 단계와, 상기 제 1 폴리실리콘을 건식식각한 후 잔류 포토레지스트를 제거하는 단계를 포함하는 것을 특징으로 하는 캐패시터의 전하저장 전극 형성 방법.
  2. 제1항에 있어서, 상기 제 1 및 제 2 폴리실리콘층의 두께는 약 900Å 내지 1100Å인 것을 특징으로 하는 캐패시터의 전하저장 전극형성방법.
  3. 제1항 또는 제2항에 있어서, 상기 제 1 및 제 2 폴리실리콘은 약 575℃ 내지 585℃온도, 100mTorr 압력에서 약 100㎤ 내지 200㎤의 실란가스를 이용하여 증착하여 반구형 입자 폴리실리콘층인 것을 특징으로 하는 캐패시터의 전하저장 전극 형성 방법.
  4. 제1항에 있어서, 상기 제 1 및 제 2 폴리실리콘층을 증착하는 두께는 약 1100Å 내지 1300Å인 것을 특징으로 하는 캐패시터의 전하저장 전극형성방법.
  5. 제4항에 있어서, 상기 제 1 및 제 2 폴리실리콘을 증착하는 각 단계 이후에 열산화시킨 후 형성된 산화막을 제거하는 단계를 더 포함하는 것을 특징으로 하는 캐패시터의 전하저장 전극 형성 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950034844A 1995-10-11 1995-10-11 캐패시터의 전하저장 전극 형성 방법 KR970024139A (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950034844A KR970024139A (ko) 1995-10-11 1995-10-11 캐패시터의 전하저장 전극 형성 방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950034844A KR970024139A (ko) 1995-10-11 1995-10-11 캐패시터의 전하저장 전극 형성 방법

Publications (1)

Publication Number Publication Date
KR970024139A true KR970024139A (ko) 1997-05-30

Family

ID=66583551

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950034844A KR970024139A (ko) 1995-10-11 1995-10-11 캐패시터의 전하저장 전극 형성 방법

Country Status (1)

Country Link
KR (1) KR970024139A (ko)

Similar Documents

Publication Publication Date Title
KR0154161B1 (ko) 반도체소자의 캐패시터 제조방법
KR940010322A (ko) 반도체 메모리셀의 캐패시터 전극 제조방법
KR970024139A (ko) 캐패시터의 전하저장 전극 형성 방법
KR970024178A (ko) 캐패시터의 전하저장 전극 형성 방법
KR960003772B1 (ko) 반도체 소자의 캐패시터 제조방법
KR0148332B1 (ko) 캐패시터의 다층 전하저장 전극 형성 방법
KR0151257B1 (ko) 반도체 메모리장치 제조방법
KR100271792B1 (ko) 캐패시터형성방법
KR100228370B1 (ko) 반도체 장치의 캐패시터 형성방법
KR100442779B1 (ko) 디램 소자의 제조방법
KR950012031B1 (ko) 캐패시터의 전하저장전극 형성방법
KR100304948B1 (ko) 반도체메모리장치제조방법
KR950010075A (ko) 터널형 캐패시터구조를 갖는 디램셀 제조방법
KR0130544B1 (ko) 반도체 소자의 캐패시터 제조방법
KR960006721B1 (ko) 스택 캐패시터 제조방법
KR100232161B1 (ko) 반도체 메모리장치 제조방법
KR970000220B1 (ko) 디램(dram)셀 커패시터 제조방법
KR100215862B1 (ko) 반도체 소자의 캐패시터 구조 및 제조방법
KR100269608B1 (ko) 캐패시터 형성방법
KR950034630A (ko) 반도체소자의 저장전극 형성방법
KR940027172A (ko) 디램셀의 스택캐패시터 제조방법
KR970012990A (ko) 자기 정렬을 이용한 커패시터 제조방법
KR970024179A (ko) 캐패시터의 전하저장 전극 형성 방법
KR930022554A (ko) 메모리 커패시터의 구조 및 제조방법
KR960002852A (ko) 반도체소자의 캐패시터 제조방법

Legal Events

Date Code Title Description
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid