KR970008514A - 반도체장치, 반도체장치용 인터포우저(interposer) 및 그 제조방법 - Google Patents
반도체장치, 반도체장치용 인터포우저(interposer) 및 그 제조방법 Download PDFInfo
- Publication number
- KR970008514A KR970008514A KR1019960028982A KR19960028982A KR970008514A KR 970008514 A KR970008514 A KR 970008514A KR 1019960028982 A KR1019960028982 A KR 1019960028982A KR 19960028982 A KR19960028982 A KR 19960028982A KR 970008514 A KR970008514 A KR 970008514A
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- South Korea
- Prior art keywords
- stud
- conductive type
- substrate
- semiconductor device
- interposer
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims abstract 13
- 238000007747 plating Methods 0.000 claims abstract 7
- 239000011347 resin Substances 0.000 claims abstract 6
- 229920005989 resin Polymers 0.000 claims abstract 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims abstract 2
- 229910052709 silver Inorganic materials 0.000 claims abstract 2
- 239000004332 silver Substances 0.000 claims abstract 2
- 239000002184 metal Substances 0.000 claims 5
- 229910052751 metal Inorganic materials 0.000 claims 5
- 238000000034 method Methods 0.000 claims 5
- 238000005530 etching Methods 0.000 claims 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 238000001746 injection moulding Methods 0.000 claims 1
- 239000000463 material Substances 0.000 abstract 1
Classifications
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Abstract
절연레진 재료의 기판(1)에 있어서, 기판(1)의 중앙에 반도체칩(2)을 설치하고, 다수의 좋은 스터드를 칩(2) 부근의 기판(1)에 매립한다.
본딩패드(13) 및 랜드(14)는 실버 플레이팅에 의해 각 스터드(12)의 양단 평면상에 형성된다.
랜드(14)의 평면과 기판의 배면측 평면이 거의 동일 평면상에 있도록 스터드(12)의 길이가 결정되지만, 그것은 보다 길어도 좋다.
본딩패드(12) 및 랜드(14)를 가진 스터드(12)를 포함하는 기판(1)은 인터포우저(15)로서 규정된다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 본 발명에 따른 제1의 실시예에 있어서의 인터포저 및 반도체장치를 나타내는 단면도, 제7도는 본 발명에 따른 제1의 실시예에 있어서의 언터포우저의 프리폼의 제조방법을 나타내는 설명도.
Claims (15)
- 기판과: 상기 기판상에 실장된 반도체칩과; 입출력단자로서 상기 반도체칩 부근에 배열된 복수의 도전형의 스터드와; 상기 도전형의 스터드 각각에 상기 반도체칩상의 본딩패드를 접속하기 위한 복수의 본딩와이어를 구비하고, 상기 도전형의 스터드의 양측 평면은 상기 기판의 표면과 배면측 평면으로부터 노출되고, 그에 의해 상기 사이드 평면이 본딩패드 및 랜드로서 작용하는 반도체장치.
- 제1항에 있어서, 상기 도전형 스터드의 적어도 하나의 사이드 평면은 와이어본딩을 위해 도금되는 반도체장치.
- 제1항에 있어서, 상기 기판은 절연레진으로 이루어져 있고, 상기 도전형의 스터드는 상기 기판에 성형된 좋은 와이어인 반도체장치.
- 제1항에 있어서, 상기 도전형의 스터드는 나사모양의 스터드인 반도체장치.
- 반도체칩이 실장되는 다이패드를 가진 기판과, 입출력단자로서 상기 다이패드 부근에 배열된 복수의 도전형의 스터드를 구비하고, 상기 도전형의 스터드의 양측 평면은 상기 기판의 표면과 배면측 평면으로부터 노출되고, 그에 의해 상기 사이드 평면이 본딩패드 및 랜드로서 작용하는 반도체장치.
- 제5항에 있어서, 상기 도전형의 스터드의 적어도 하나의 사이드 평면은 와이어본딩을 위해 도금되는 반도체장치용 인터포우저.
- 제5항에 있어서, 상기 기판은 절연레진으로 이루어져 있고, 상기 도전형의 스터드는 상기 기판에 성형된 좋은 와이어인 반도체장치용 인터포우저.
- 제5항에 있어서, 상기 도전형의 스터드는 나사모양의 스터드인 반도체장치용 인터포우저.
- 복수의 와이어를 준비하는 스텝과, 프리폼의 일정 길이를 얻기 위해 소정의 배열로 상기 와이어중의 한개의 절연재료가 사출 성형되는 스텝과, 상기 프리폼을 인터포우저로 분할하는 스텝을 구비한 반도체장치용 인터포우저의 제조방법.
- 반도체장치용 인터포우저의 제조방법에 있어서, 금속플레이트를 준비하는 스텝과, 상기 금속플레이트의 양측상에 복수의 플레이팅패드를 도금하는 스텝과, 에칭액에 대비하여 마스크로서 상기 플레이팅패드를 사용함으로써 그 표면으로부터 상기 금속플레이트를 에칭하는 스텝과 상기 플레이팅패드의 표면을 노출하도록 상기 금속플레이트의 에치부로 레진을 주입하는 스텝과, 상기 레진의 배면측만큼 깊게 그 배면측으로부터 상기 금속플레이틀르 에칭하는 스텝을 구비한 방법.
- 제10항에 있어서, 상기 플레이팅은 골드 또는 실버플레이팅인 반도체 장치용 인터포우저의 제조방법.
- 복수의 홀이 설치되는 기판을 준비하는 스텝과, 각 홀에 도전형의 스터드를 삽입하는 스텝을 구비한 반도체장치용 인터포우저의 제조방법.
- 제12항에 있어서, 상기 도전형의 스터드는 프리폼된 나사모양의 스터드인 반반도체장치용 인터포우저의 제조방법.
- jig배열로 복수의 도전형의 스터드를 배열하는 스텝과, 상기 각 스터드의 양단이 노출되도록 상기 jig로 용해된 절연레진을 흘리는 스텝을 구비한 반도체장치용 인터포우저의 제조방법.
- 제14항에 있어서, 상기 도전형의 스터드는 프리폼된 나사모양의 스터드인 반도체장치용 인터포우저의 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
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JP95-181376 | 1995-07-18 | ||
JP18137695A JP3264147B2 (ja) | 1995-07-18 | 1995-07-18 | 半導体装置、半導体装置用インターポーザ及びその製造方法 |
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TW201021119A (en) * | 2008-09-25 | 2010-06-01 | Lg Innotek Co Ltd | Structure and manufacture method for multi-row lead frame and semiconductor package |
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JPS633160A (ja) * | 1986-06-20 | 1988-01-08 | 松下冷機株式会社 | 冷蔵庫 |
JP2840316B2 (ja) * | 1989-09-06 | 1998-12-24 | 新光電気工業株式会社 | 半導体装置およびその製造方法 |
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US5239746A (en) * | 1991-06-07 | 1993-08-31 | Norton Company | Method of fabricating electronic circuits |
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EP0582052A1 (en) * | 1992-08-06 | 1994-02-09 | Motorola, Inc. | Low profile overmolded semiconductor device and method for making the same |
KR100238197B1 (ko) * | 1992-12-15 | 2000-01-15 | 윤종용 | 반도체장치 |
JPH07142627A (ja) * | 1993-11-18 | 1995-06-02 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US5741729A (en) * | 1994-07-11 | 1998-04-21 | Sun Microsystems, Inc. | Ball grid array package for an integrated circuit |
US5508556A (en) * | 1994-09-02 | 1996-04-16 | Motorola, Inc. | Leaded semiconductor device having accessible power supply pad terminals |
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-
1995
- 1995-07-18 JP JP18137695A patent/JP3264147B2/ja not_active Expired - Fee Related
-
1996
- 1996-07-17 TW TW085108661A patent/TW326622B/zh active
- 1996-07-18 KR KR1019960028982A patent/KR970008514A/ko not_active Application Discontinuation
- 1996-07-18 US US08/683,156 patent/US5866948A/en not_active Expired - Fee Related
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1997
- 1997-07-18 US US08/896,836 patent/US6031292A/en not_active Expired - Fee Related
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JPH0936168A (ja) | 1997-02-07 |
TW326622B (en) | 1998-02-11 |
US6031292A (en) | 2000-02-29 |
US5866948A (en) | 1999-02-02 |
JP3264147B2 (ja) | 2002-03-11 |
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