KR970008514A - 반도체장치, 반도체장치용 인터포우저(interposer) 및 그 제조방법 - Google Patents

반도체장치, 반도체장치용 인터포우저(interposer) 및 그 제조방법 Download PDF

Info

Publication number
KR970008514A
KR970008514A KR1019960028982A KR19960028982A KR970008514A KR 970008514 A KR970008514 A KR 970008514A KR 1019960028982 A KR1019960028982 A KR 1019960028982A KR 19960028982 A KR19960028982 A KR 19960028982A KR 970008514 A KR970008514 A KR 970008514A
Authority
KR
South Korea
Prior art keywords
stud
conductive type
substrate
semiconductor device
interposer
Prior art date
Application number
KR1019960028982A
Other languages
English (en)
Inventor
하지메 무라카미
마모루 미타
토요히코 쿠마쿠라
노리오 오카베
카츠지 코마츠
쇼우지 신자와
Original Assignee
하라 세이지
히다찌 케이블 리미티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 하라 세이지, 히다찌 케이블 리미티드 filed Critical 하라 세이지
Publication of KR970008514A publication Critical patent/KR970008514A/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48644—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48844—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10378—Interposers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0369—Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process

Abstract

절연레진 재료의 기판(1)에 있어서, 기판(1)의 중앙에 반도체칩(2)을 설치하고, 다수의 좋은 스터드를 칩(2) 부근의 기판(1)에 매립한다.
본딩패드(13) 및 랜드(14)는 실버 플레이팅에 의해 각 스터드(12)의 양단 평면상에 형성된다.
랜드(14)의 평면과 기판의 배면측 평면이 거의 동일 평면상에 있도록 스터드(12)의 길이가 결정되지만, 그것은 보다 길어도 좋다.
본딩패드(12) 및 랜드(14)를 가진 스터드(12)를 포함하는 기판(1)은 인터포우저(15)로서 규정된다.

Description

반도체장치, 반도체장치용 인터포우저(interposer) 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 본 발명에 따른 제1의 실시예에 있어서의 인터포저 및 반도체장치를 나타내는 단면도, 제7도는 본 발명에 따른 제1의 실시예에 있어서의 언터포우저의 프리폼의 제조방법을 나타내는 설명도.

Claims (15)

  1. 기판과: 상기 기판상에 실장된 반도체칩과; 입출력단자로서 상기 반도체칩 부근에 배열된 복수의 도전형의 스터드와; 상기 도전형의 스터드 각각에 상기 반도체칩상의 본딩패드를 접속하기 위한 복수의 본딩와이어를 구비하고, 상기 도전형의 스터드의 양측 평면은 상기 기판의 표면과 배면측 평면으로부터 노출되고, 그에 의해 상기 사이드 평면이 본딩패드 및 랜드로서 작용하는 반도체장치.
  2. 제1항에 있어서, 상기 도전형 스터드의 적어도 하나의 사이드 평면은 와이어본딩을 위해 도금되는 반도체장치.
  3. 제1항에 있어서, 상기 기판은 절연레진으로 이루어져 있고, 상기 도전형의 스터드는 상기 기판에 성형된 좋은 와이어인 반도체장치.
  4. 제1항에 있어서, 상기 도전형의 스터드는 나사모양의 스터드인 반도체장치.
  5. 반도체칩이 실장되는 다이패드를 가진 기판과, 입출력단자로서 상기 다이패드 부근에 배열된 복수의 도전형의 스터드를 구비하고, 상기 도전형의 스터드의 양측 평면은 상기 기판의 표면과 배면측 평면으로부터 노출되고, 그에 의해 상기 사이드 평면이 본딩패드 및 랜드로서 작용하는 반도체장치.
  6. 제5항에 있어서, 상기 도전형의 스터드의 적어도 하나의 사이드 평면은 와이어본딩을 위해 도금되는 반도체장치용 인터포우저.
  7. 제5항에 있어서, 상기 기판은 절연레진으로 이루어져 있고, 상기 도전형의 스터드는 상기 기판에 성형된 좋은 와이어인 반도체장치용 인터포우저.
  8. 제5항에 있어서, 상기 도전형의 스터드는 나사모양의 스터드인 반도체장치용 인터포우저.
  9. 복수의 와이어를 준비하는 스텝과, 프리폼의 일정 길이를 얻기 위해 소정의 배열로 상기 와이어중의 한개의 절연재료가 사출 성형되는 스텝과, 상기 프리폼을 인터포우저로 분할하는 스텝을 구비한 반도체장치용 인터포우저의 제조방법.
  10. 반도체장치용 인터포우저의 제조방법에 있어서, 금속플레이트를 준비하는 스텝과, 상기 금속플레이트의 양측상에 복수의 플레이팅패드를 도금하는 스텝과, 에칭액에 대비하여 마스크로서 상기 플레이팅패드를 사용함으로써 그 표면으로부터 상기 금속플레이트를 에칭하는 스텝과 상기 플레이팅패드의 표면을 노출하도록 상기 금속플레이트의 에치부로 레진을 주입하는 스텝과, 상기 레진의 배면측만큼 깊게 그 배면측으로부터 상기 금속플레이틀르 에칭하는 스텝을 구비한 방법.
  11. 제10항에 있어서, 상기 플레이팅은 골드 또는 실버플레이팅인 반도체 장치용 인터포우저의 제조방법.
  12. 복수의 홀이 설치되는 기판을 준비하는 스텝과, 각 홀에 도전형의 스터드를 삽입하는 스텝을 구비한 반도체장치용 인터포우저의 제조방법.
  13. 제12항에 있어서, 상기 도전형의 스터드는 프리폼된 나사모양의 스터드인 반반도체장치용 인터포우저의 제조방법.
  14. jig배열로 복수의 도전형의 스터드를 배열하는 스텝과, 상기 각 스터드의 양단이 노출되도록 상기 jig로 용해된 절연레진을 흘리는 스텝을 구비한 반도체장치용 인터포우저의 제조방법.
  15. 제14항에 있어서, 상기 도전형의 스터드는 프리폼된 나사모양의 스터드인 반도체장치용 인터포우저의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960028982A 1995-07-18 1996-07-18 반도체장치, 반도체장치용 인터포우저(interposer) 및 그 제조방법 KR970008514A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP95-181376 1995-07-18
JP18137695A JP3264147B2 (ja) 1995-07-18 1995-07-18 半導体装置、半導体装置用インターポーザ及びその製造方法

Publications (1)

Publication Number Publication Date
KR970008514A true KR970008514A (ko) 1997-02-24

Family

ID=16099654

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960028982A KR970008514A (ko) 1995-07-18 1996-07-18 반도체장치, 반도체장치용 인터포우저(interposer) 및 그 제조방법

Country Status (4)

Country Link
US (2) US5866948A (ko)
JP (1) JP3264147B2 (ko)
KR (1) KR970008514A (ko)
TW (1) TW326622B (ko)

Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6734545B1 (en) * 1995-11-29 2004-05-11 Hitachi, Ltd. BGA type semiconductor device and electronic equipment using the same
US20040124545A1 (en) * 1996-12-09 2004-07-01 Daniel Wang High density integrated circuits and the method of packaging the same
EP0860876A3 (de) * 1997-02-21 1999-09-22 DaimlerChrysler AG Anordnung und Verfahren zur Herstellung von CSP-Gehäusen für elektrische Bauteile
JP3837215B2 (ja) * 1997-10-09 2006-10-25 三菱電機株式会社 個別半導体装置およびその製造方法
JPH11284006A (ja) * 1998-03-31 1999-10-15 Fujitsu Ltd 半導体装置
US6299456B1 (en) 1998-04-10 2001-10-09 Micron Technology, Inc. Interposer with contact structures for electrical testing
US6137167A (en) * 1998-11-24 2000-10-24 Micron Technology, Inc. Multichip module with built in repeaters and method
US6077766A (en) * 1999-06-25 2000-06-20 International Business Machines Corporation Variable thickness pads on a substrate surface
JP3526788B2 (ja) 1999-07-01 2004-05-17 沖電気工業株式会社 半導体装置の製造方法
US6248001B1 (en) * 1999-08-06 2001-06-19 Micron Technology, Inc. Semiconductor die de-processing using a die holder and chemical mechanical polishing
US6319829B1 (en) * 1999-08-18 2001-11-20 International Business Machines Corporation Enhanced interconnection to ceramic substrates
US6404059B1 (en) * 2000-02-08 2002-06-11 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having a mounting structure and fabrication method thereof
US6399415B1 (en) 2000-03-20 2002-06-04 National Semiconductor Corporation Electrical isolation in panels of leadless IC packages
US6686652B1 (en) 2000-03-20 2004-02-03 National Semiconductor Locking lead tips and die attach pad for a leadless package apparatus and method
US6372539B1 (en) 2000-03-20 2002-04-16 National Semiconductor Corporation Leadless packaging process using a conductive substrate
US6452255B1 (en) * 2000-03-20 2002-09-17 National Semiconductor, Corp. Low inductance leadless package
US6396710B1 (en) * 2000-05-12 2002-05-28 Raytheon Company High density interconnect module
JP3442721B2 (ja) 2000-05-24 2003-09-02 沖電気工業株式会社 半導体装置
JP2001338947A (ja) * 2000-05-26 2001-12-07 Nec Corp フリップチップ型半導体装置及びその製造方法
TW507482B (en) * 2000-06-09 2002-10-21 Sanyo Electric Co Light emitting device, its manufacturing process, and lighting device using such a light-emitting device
TW506236B (en) * 2000-06-09 2002-10-11 Sanyo Electric Co Method for manufacturing an illumination device
US6683368B1 (en) * 2000-06-09 2004-01-27 National Semiconductor Corporation Lead frame design for chip scale package
CA2417172C (en) * 2000-07-07 2010-10-12 Cosmo Plant Co., Ltd. Plant cultivating method, cultivating device, and its lighting device
US6689640B1 (en) 2000-10-26 2004-02-10 National Semiconductor Corporation Chip scale pin array
US6489571B1 (en) * 2000-10-31 2002-12-03 Lsi Logic Corporation Molded tape ball grid array package
US6770959B2 (en) * 2000-12-15 2004-08-03 Silconware Precision Industries Co., Ltd. Semiconductor package without substrate and method of manufacturing same
US6348726B1 (en) 2001-01-18 2002-02-19 National Semiconductor Corporation Multi row leadless leadframe package
KR100445072B1 (ko) * 2001-07-19 2004-08-21 삼성전자주식회사 리드 프레임을 이용한 범프 칩 캐리어 패키지 및 그의제조 방법
US20070108609A1 (en) * 2001-07-19 2007-05-17 Samsung Electronics Co., Ltd. Bumped chip carrier package using lead frame and method for manufacturing the same
JP2003204015A (ja) 2002-01-10 2003-07-18 Oki Electric Ind Co Ltd 半導体装置、半導体装置の製造方法、及びインターポーザ基板の製造方法
DE10205544A1 (de) * 2002-02-11 2003-05-15 Infineon Technologies Ag Verfahren zur Herstellung eines elektronischen Halbleiterbauteils mit dreidimensionaler Umverdrahtungsstruktur sowie elektronisches Halbleiterbauteil
JP4253475B2 (ja) * 2002-07-04 2009-04-15 パイオニア株式会社 発光素子駆動用半導体装置
US6737931B2 (en) * 2002-07-19 2004-05-18 Agilent Technologies, Inc. Device interconnects and methods of making the same
JP4159431B2 (ja) * 2002-11-15 2008-10-01 株式会社ルネサステクノロジ 半導体装置の製造方法
US6839965B2 (en) * 2003-02-06 2005-01-11 R-Tec Corporation Method of manufacturing a resistor connector
US7060535B1 (en) * 2003-10-29 2006-06-13 Ns Electronics Bangkok (1993) Ltd. Flat no-lead semiconductor die package including stud terminals
US7105918B2 (en) * 2004-07-29 2006-09-12 Micron Technology, Inc. Interposer with flexible solder pad elements and methods of manufacturing the same
US7095096B1 (en) 2004-08-16 2006-08-22 National Semiconductor Corporation Microarray lead frame
US7846775B1 (en) 2005-05-23 2010-12-07 National Semiconductor Corporation Universal lead frame for micro-array packages
JP2008245244A (ja) * 2007-02-26 2008-10-09 Sony Corp 撮像素子パッケージ、撮像素子モジュールおよびレンズ鏡筒並びに撮像装置
JP5089336B2 (ja) * 2007-10-29 2012-12-05 新光電気工業株式会社 パッケージ用シリコン基板
WO2010036051A2 (en) * 2008-09-25 2010-04-01 Lg Innotek Co., Ltd. Structure and manufacture method for multi-row lead frame and semiconductor package
US7982305B1 (en) * 2008-10-20 2011-07-19 Maxim Integrated Products, Inc. Integrated circuit package including a three-dimensional fan-out / fan-in signal routing
TWI372454B (en) * 2008-12-09 2012-09-11 Advanced Semiconductor Eng Quad flat non-leaded package and manufacturing method thereof
DE102009042479A1 (de) * 2009-09-24 2011-03-31 Msg Lithoglas Ag Verfahren zum Herstellen einer Anordnung mit einem Bauelement auf einem Trägersubstrat und Anordnung sowie Verfahren zum Herstellen eines Halbzeuges und Halbzeug
TWI469289B (zh) 2009-12-31 2015-01-11 矽品精密工業股份有限公司 半導體封裝結構及其製法
US8304900B2 (en) * 2010-08-11 2012-11-06 Stats Chippac Ltd. Integrated circuit packaging system with stacked lead and method of manufacture thereof
CN103824836B (zh) * 2010-08-31 2017-03-01 先进封装技术私人有限公司 半导体承载元件及半导体封装件
CN103824821B (zh) * 2014-03-11 2016-04-06 湖南进芯电子科技有限公司 一种塑料密闭封装的开关电源模块及其制备方法
TW201539674A (zh) * 2014-04-10 2015-10-16 Chipmos Technologies Inc 四方扁平無引腳封裝及其製造方法
US10747702B2 (en) * 2018-10-31 2020-08-18 Dell Products L.P. Interposer systems for information handling systems

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS633160A (ja) * 1986-06-20 1988-01-08 松下冷機株式会社 冷蔵庫
JP2840316B2 (ja) * 1989-09-06 1998-12-24 新光電気工業株式会社 半導体装置およびその製造方法
JP3096816B2 (ja) * 1990-03-16 2000-10-10 住友金属工業株式会社 電気的接続部材の製造方法
KR930001365A (ko) * 1991-03-27 1993-01-16 빈센트 죠셉 로너 복합 플립 칩 반도체 소자와 그 제조 및 번-인(burning-in) 방법
US5239746A (en) * 1991-06-07 1993-08-31 Norton Company Method of fabricating electronic circuits
JPH0563109A (ja) * 1991-08-29 1993-03-12 New Japan Radio Co Ltd モールド型ｉｃパツケージ
JPH05144995A (ja) * 1991-11-18 1993-06-11 Matsushita Electric Works Ltd 半導体パツケージ
JP3480950B2 (ja) * 1992-04-02 2003-12-22 新光電気工業株式会社 半導体装置と半導体装置用フイルムキャリア
EP0582052A1 (en) * 1992-08-06 1994-02-09 Motorola, Inc. Low profile overmolded semiconductor device and method for making the same
KR100238197B1 (ko) * 1992-12-15 2000-01-15 윤종용 반도체장치
JPH07142627A (ja) * 1993-11-18 1995-06-02 Fujitsu Ltd 半導体装置及びその製造方法
US5741729A (en) * 1994-07-11 1998-04-21 Sun Microsystems, Inc. Ball grid array package for an integrated circuit
US5508556A (en) * 1994-09-02 1996-04-16 Motorola, Inc. Leaded semiconductor device having accessible power supply pad terminals
US5581444A (en) * 1995-07-26 1996-12-03 Harris Corporation Device and method for enhancing thermal and high frequency performance of integrated circuit packages

Also Published As

Publication number Publication date
JP3264147B2 (ja) 2002-03-11
US5866948A (en) 1999-02-02
TW326622B (en) 1998-02-11
US6031292A (en) 2000-02-29
JPH0936168A (ja) 1997-02-07

Similar Documents

Publication Publication Date Title
KR970008514A (ko) 반도체장치, 반도체장치용 인터포우저(interposer) 및 그 제조방법
US6294830B1 (en) Microelectronic assembly with conductive terminals having an exposed surface through a dielectric layer
US4677526A (en) Plastic pin grid array chip carrier
KR0159987B1 (ko) 솔더볼을 입출력 단자로 사용하는 볼그리드 어레이(bga) 반도체 패캐지의 열 방출구조
US7511361B2 (en) DFN semiconductor package having reduced electrical resistance
US8659146B2 (en) Lead frame based, over-molded semiconductor package with integrated through hole technology (THT) heat spreader pin(s) and associated method of manufacturing
KR920010853A (ko) 수지봉지형 반도체장치
US6002173A (en) Semiconductor device package with metal-polymer joint of controlled roughness
KR100336080B1 (ko) 반도체 장치 및 그 제조방법
KR970067805A (ko) 반도체장치 및 그 제조방법
KR950015727A (ko) 반도체 장치 및 그 제조방법
KR970024069A (ko) 반도체장치 및 그 제조방법(semiconductor device and method of manufacturing semiconductor device)
KR960012397A (ko) 칩 사이즈 패키지형 반도체 장치의 제조 방법
US4987474A (en) Semiconductor device and method of manufacturing the same
US6965159B1 (en) Reinforced lead-frame assembly for interconnecting circuits within a circuit module
KR20010070056A (ko) 반도체 장치 제조 공정 및 반도체 장치
KR960039305A (ko) 반도체 장치 및 그 제조 방법
US6037662A (en) Chip scale package
KR940008061A (ko) 기판상의 칩 어셈블리 및 이의 제조 방법
US5393705A (en) Molded semiconductor device using intermediate lead pattern on film carrier formed from lattice pattern commonly available for devices and process of fabrication thereof
KR100281298B1 (ko) 볼그리드어레이용리드프레임과,그것을이용한반도체장치및그제조방법
KR100186759B1 (ko) 솔더볼을 입출력 단자로 사용하는 볼 그리드 어레이(bga) 반도체 패키지의 열 방출구조
KR100291511B1 (ko) 멀티 칩 패키지
JP4450800B2 (ja) 半導体装置の製造方法
JPH09214093A (ja) 実装回路装置およびその製造方法

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application