KR970008404A - 반도체 소자의 금속층간절연막 형성방법 - Google Patents

반도체 소자의 금속층간절연막 형성방법 Download PDF

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Publication number
KR970008404A
KR970008404A KR1019950020270A KR19950020270A KR970008404A KR 970008404 A KR970008404 A KR 970008404A KR 1019950020270 A KR1019950020270 A KR 1019950020270A KR 19950020270 A KR19950020270 A KR 19950020270A KR 970008404 A KR970008404 A KR 970008404A
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South Korea
Prior art keywords
film
forming
contact hole
semiconductor device
entire upper
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KR1019950020270A
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English (en)
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KR100312376B1 (ko
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이주일
김광수
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김주용
현대전자산업 주식회사
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Priority to KR1019950020270A priority Critical patent/KR100312376B1/ko
Publication of KR970008404A publication Critical patent/KR970008404A/ko
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Publication of KR100312376B1 publication Critical patent/KR100312376B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 금속층간절연막 형성방법에 관한 것으로, 콘택홀내에서 금속층과 SOG 막의 접촉으로 인한 포이즌 비아(Poisoned via)의 발생을 방지하기 위하여 SOG 막을 도포하기 전에 콘택홀 내부를 감광막으로 매립시키므로써 금속층의 불량을 방지하여 소자의 전기적특성이 향상될 수 있도록 한 반도체 소자의 금속층간절연막 형성방법에 관한 것이다.

Description

반도체 소자의 금속층간절연막 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2A 내지 제2E도는 본 발명에 따른 반도체 소자의 금속층간절연막 형성방법을 설명하기 위한 소자의 단면도.

Claims (1)

  1. 반도체 소자의 금속층간절연막 형성방법에 있어서, 접합부가 형성된 실리콘기판상에 절연막을 형성하는 단계와, 상기 단계로부터 전체 상부면에 제1감광막을 도포한 후 콘택 마스트를 이용하여 상기 제1감광막을 패터닝하고, 상기 패터닝된 제1감광막을 마스크로 이용한 식각공정으로 상기 절연막을 식각하여 상기 접합부가 노출되도록 콘택홀을 형성하는 단계와, 상기 단계로부터 상기 제1감광막을 제거한 후 전체 상부면에 금속층을 형성하는 단계와, 상기 단계로부터 금속배선용 마스크를 이용한 사진 및 식각공정으로 상기 금속층을 패터닝한 후 전체 상부면에 제1금속층간절연막을 형성하는 단계와, 상기 단계로부터 상기 콘택홀 내부가 매립되도록 전체 상부면에 제2감광막을 도포한 후 상기 금속배선용 마스크를 이용하여 상기 제2감광막을 패터닝하는 단계와, 상기 단계로부터 전체 상부면에 SOG 막을 두껍게 형성하여 표면을 평탄화시키는 단계와, 상기 단계로부터 상기 SOG막 및 제2감광막을 상기 제1금속층간절연막의 표면이 노출되는 시점까지 전면식각하는 단계와, 상기 단계로부터 상기 콘택홀 내부에 잔류되는 제2감광막을 제거한 후 상기 콘택홀 내부가 매립되도록 전체 상부면에 제2금속층간절연막을 형성하 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 금속층간절연막 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950020270A 1995-07-11 1995-07-11 반도체소자의금속층간절연막형성방법 KR100312376B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950020270A KR100312376B1 (ko) 1995-07-11 1995-07-11 반도체소자의금속층간절연막형성방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950020270A KR100312376B1 (ko) 1995-07-11 1995-07-11 반도체소자의금속층간절연막형성방법

Publications (2)

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KR970008404A true KR970008404A (ko) 1997-02-24
KR100312376B1 KR100312376B1 (ko) 2003-08-06

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KR1019950020270A KR100312376B1 (ko) 1995-07-11 1995-07-11 반도체소자의금속층간절연막형성방법

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Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5844747A (ja) * 1981-09-10 1983-03-15 Toshiba Corp 半導体装置およびその製造方法
JPH077801B2 (ja) * 1987-10-13 1995-01-30 日本電気株式会社 半導体装置の製造方法
KR920010874A (ko) * 1990-11-23 1992-06-27 정몽헌 반도체 소자의 다층배선 제조방법
KR100237016B1 (ko) * 1993-10-12 2000-01-15 김영환 반도체 소자의 금속배선 제조방법

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