KR970004875A - 신호 처리 장치 및 방법 - Google Patents

신호 처리 장치 및 방법 Download PDF

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KR970004875A
KR970004875A KR1019960007834A KR19960007834A KR970004875A KR 970004875 A KR970004875 A KR 970004875A KR 1019960007834 A KR1019960007834 A KR 1019960007834A KR 19960007834 A KR19960007834 A KR 19960007834A KR 970004875 A KR970004875 A KR 970004875A
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signal
circuit
data
latch
output
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피터 제이. 클레이든 안쏘니
디. 맥팔레인 찰스
제이. 갬맥 리차드
마크 존스 안쏘니
피. 로빈스 윌리엄
바네스 마크
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데니스 피셸
디스커비젼 어소우쉬에이트
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Publication of KR970004875A publication Critical patent/KR970004875A/ko

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Abstract

다중 레벨의 잔유 측방을 활용하기 위한 집적화된 디지탈 통신 시스템을 제공한다. 통신 시스템은 제한된 대역폭 채널로부터 다중 레벨 펄스 진폭 변조된 디지탈 신호를 수신한다. 이 시스템은 디지탈 데이타를 복구하기 전에 입력 신호를 변조하고 샘플하고 필터하는 처리 단계를 포함한다. 다른 단계는 타이밍을 복구하고, 전송된 신호의 주파수와 위상을 잠그고, 자동 이득 제어를 제공한다. 적응 등화기, 에러 교정 회로 출력 인터페이스가 디지탈 데이타를 복구하고, 다른 장치에 전송하기 위하여 제공된다.

Description

신호 처리 장치 및 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에서 구현된 통신 시스템의 블럭도이다.

Claims (13)

  1. 미리 전송하는 특성을 가진 변조 신호로서 채널을 통하여 전송된 데이타 패킷을 수신하기 위한 신호 처리 장치에 있어서, 샘플링 구간에서 입력 신호를 샘플하고, ADC 출력을 가지는 아날로그 디지탈 변환기, 상기 샘플링 구간의 주파수와 위상을 조절하기 위하여 상기 ADC 출력에 연결된 타이밍 복구 회로, 상기 입력 신호의 주파수와 위상을 조절하기 위하여 상기 ADC 출력에 연결된 캐리어 복구 외로, 상기 입력 신호를 미리 전송하는 특성에 상기 ADC 출력의 특성을 매치하기 위한 필터, 상기 필터에 연결된 적응 등화기, 상기 적응 등화기에 연결된 에러 교정회로, 상기 에러 교정 회로에 연결된 출력 인터페이스, 상기 타이밍 복구 회로, 상기 캐리어 복구 회로 상기 등화기 상기 에러 교정 회로와 상기 출력 인터페이스가 반도체 집적회로로 구성된 것을 특징으로 하는 신호 처리 장치.
  2. 제1항에 따른 장치에 있어서, 상기 변조 신호가 잔유 측방 변조에 의해 변조되고, 상기 채널에 연결되고 상기 변조 신호 파형을 입력받는 증폭기 상기 증폭기에 연결되고 복조 신호를 생성하는 복조기로 구성된 것을 특징으로 하는 신호 처리 장치.
  3. 제1항과 제2항에 따른 장치에 있어, 다수의 상기 데이타 패킷이 프레임내에 그룹되고, 각 상기 프레임이 프레임 헤더와 상기 프레임 헤더내의 훈련 스퀸스를 구성하는 것을 특징으로 하는 신호 장치.
  4. 제1항에 있어서 제3항에 따른 장치에 있어서, 상기 등화기가 제1응답 필터, 상기 제1응답 필터의 계수를 조절하고, 상기 제1응답 필터의 출력과 상기 훈련 시퀸스간의 차이로부터 유도된 에러 신호에 응답하기 위한 회로로 구성된 것을 특징으로 하는 신호 장치.
  5. 제1항에서 제4항에 따른 장치에 있어서, 상기 계수를 조절하기 위한 상기 회로가 최소 평균 자승 알고리즘을 실행하기 위한 수단으로 구성된 것을 특징으로 하는 신호 처리 장치.
  6. 제1항에서 제5항에 따른 장치에 있어서, 상기 등화기가 다음 공식에 따라 상기 변조 신호를 나타내는 위상 요소와 직교 요소를 생성하기 위한 위상 트랙킹 회로,
    여기에서, data는 출력이고, Φ는 위상 에러이고, a(t)는 전송 데이타이고,는 a(t)의 직교 요소이고; 다음 공식에 따른 상기 위상 트랙킹 회로 출력.
    여기에서 θ는 상기 변조 신호 군집의 회전 각도이고, 상기 위상 트랙킹 회로가 제2응답 필터, 상기 최소 평균 자승 알고리즘에 따라 상기 각도 θ를 추정하기 위한 상기 제2응답 필터를 포함하는 회로수단으로 구성된 것을 특징으로 하는 신호 처리 장치.
  7. 제1항에서 제6항에 따른 장치에 있어서. 상기 패킷의 블럭이 삽입 깊이에 삽입되고, 상기 집적 회로에 결합된 재삽입 회로를 구성하는 장치에 있어서, 상기 삽입 패킷을 기억하고, 삽입 데이타의 블럭을 초과하지 않는 용량을 가지고, 다수의 행과 다수의 열을 가지고, 상기 열이 다수의 그룹으로 정의된 랜덤 엑세스 메모리. 상기 랜덤 엑세스 메모리의 주소의 시퀸스를 나타내는 주소 신호를 생성하고, 연속적인 주소가 스트라이브에 의해 차이가 나는 제1회로, 상기 주소 신호에 의해 결정된 상기 랜덤 엑세스 메모리의 주소에서 각각 상기 랜덤 엑세스 메모리에 그리고 메모리로부터 데이타를 연속적으로 기록하고 판독하기 위한 제2회로. 상기 삽입 깊이에 의해 상기 스트라이브가 증가하고, 상기 스트라이브가 삽입 데이타 블럭의 재삽입시에 증가 되는 제3회로로 구성된 것을 특징으로 하는 신호 처리 장치.
  8. 제1항에서 제7항에 따른 장치에 있어서, 상기 아날로그 디지탈 변화기가 상기 집적 회로내에 집적된 신호처리 장치.
  9. 제1항에서 제8항에 따른 장치에 있어서, 상기 아날로그 디지탈 변환기가 제1 및 제2유닛을 가지는 비교기를 구성하는 장치에 있어서, 각각이 상기 유닛이 제1 및 제2노드에 연결된 캐패시터,입력 전압과 참조 전압중에서 선택된 하나에 상기 제1노드를 연결하기 위한 제1스위치 수단, 상기 제2노드에 연결되고, 출력을 가지고, 상기 변환기가 상기 제2노드와 상기 출력간의 소신호 이득을 가지는 변환기,상기 제1 및 제2유닛 중에서 하나의 상기 변환기의 상기 출력을 상기 제1 및 제2유닛중에서 다른 상기 제1노드에 연결하기 위한 제2스위치 수단. 상기 제1유닛의 상기 제2스위치 수단과 상기 제2유닛의 상기 제2스위치 수단이 패쇄되고, 상기 변환기의상기 출력이 상기 입력 전압과 상기 참조 전압의 비교를 나타내는 경우에 상기 제1및 제2유닛이 양수 궤환 루프에 교차 연결된 것을 특징으로 하는 신호 처리 장치.
  10. 제1항에서 제9항에 따른 장치에 있어서, 상기 필터가 상기 입력 신호를 복소 베이스밴드 표현으로 하향 변환하고, 상기 입력 신호에서 나이키스트 동작을 수행하기 위한 필터로 구성된 것을 특징으로 하는 신호 처리 장치.
  11. 제1항에서 제11항에 따른 장치에 있어서, Berlekamp 알고리즘을 수행하기 위한 회로를 포함한 Reed-Solomon 디코우더로 구성된 상기 에러 교정 회로에 있어서, 위치 지정 다항식(x)의 일부분을 저장하기 위한 제1레지스터, D 다항식의 일부분을 저장하기 위한 제2레지스터 상기 Berlekamp 알고리즘의 연속적인 반복에서 상기 제1레지스터와 상기 제2레지스터 중에서 하나를 선택하기 위한 제1스위치 수단으로 구성된 것을 특징으로 하는 신호 처리 장치.
  12. 제1항에서 제11항에 따른 장치에 있어서, Berlekamp 알고리즘을 수행하기 위한 상기 회로에 있어서, 평가 다항식 Ω(x)의 일부분을 저장하기 위한 제3레지스터, A 다항식의 일부분을 저장하기 위한 제4레지스터, 상기 Berlekamp 알고리즘의 연속적인 반복에서 상기 제3레지스터와 상기 제4레지스터 중에서 하나를 선택하기 위한 제2스위치 수단으로 구성된 것을 특징으로 하는 신호 처리 장치.
  13. 제1항에서 제12항에 따른 장치에 있어서, 제1클럭 신호에 의해 제공된 제1클럭 비율에서 동작하는 데이타 소스로부터 제2클럭 신호에 의해 제공된 제2클럭 비율에서 동작하는 데이타 싱크에 데이타를 전송하기 위한 회로로 구성된 상기 출력 인터페이스에 있어서, 상기 제1클럭 비율에서 동작하는 제1래치, 상기 제2클럭 비율에서 동작하고, 상기 제1래치로부터 데이타를 수신하는 제2래치, 상기 제1클럭 비율에서 동작하고, 데이타 유효 신호를 생성하는 제1신호 발생기, 상기 제2클럭 비율에서 동작하고, 상기 제2클럭 신호에 응답하녀 상기 제1신호 발생기로부터 상기 데이타 유효 신호를 수신하는 적어도 하나의 제3래치, 상기 제2클럭 비율에서 동작하고, 상기 제3래치로부터 상기 데이타 유효 신호의 수신에 응답하여 상기 제2래치에 로드 데이타 신호를 활성화가는 제2신호 발생기, 상기 로드 데이타 신호가 활성화될 경우에, 상기 제2클럭 신호의 상기 제2래치의 수신에 응답하여 상기 제1래치로부터 상기 제2래치에 데이타를 전송하는 것을 특징으로 하는 출력 인터페이스.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
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US5668831A (en) 1997-09-16
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US5692020A (en) 1997-11-25
US5761210A (en) 1998-06-02
US5717715A (en) 1998-02-10
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EP0877514A2 (en) 1998-11-11
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EP0748124A2 (en) 1996-12-11
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