KR970003620A - 반도체 소자의 절연막 평탄화방법 - Google Patents

반도체 소자의 절연막 평탄화방법 Download PDF

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Publication number
KR970003620A
KR970003620A KR1019950016400A KR19950016400A KR970003620A KR 970003620 A KR970003620 A KR 970003620A KR 1019950016400 A KR1019950016400 A KR 1019950016400A KR 19950016400 A KR19950016400 A KR 19950016400A KR 970003620 A KR970003620 A KR 970003620A
Authority
KR
South Korea
Prior art keywords
insulating film
semiconductor device
film
photoresist film
exposed
Prior art date
Application number
KR1019950016400A
Other languages
English (en)
Inventor
권병인
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950016400A priority Critical patent/KR970003620A/ko
Priority to TW085107438A priority patent/TW312813B/zh
Priority to US08/665,895 priority patent/US5804514A/en
Priority to CN96110421A priority patent/CN1050693C/zh
Publication of KR970003620A publication Critical patent/KR970003620A/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H01L21/31056—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/42—Stripping or agents therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 반도체 소자의 절연막 평탄화방법에 관한 것으로, 평탄화를 향상시키기 위하여 단차가 높게 형성된 절연막상에 감광막을 도포하고 낮은 노광에너지를 이용하여 전면노광시킨 후 현상공정을 거쳐 상기 절연막의 낮은 부분에 감광막을 잔류시킨 다음 잔류된 감광막을 식각방지층으로 이용하여 노출된 절연막을 식각하므로써 평탄화를 개선시켜 소자의 수율을 향상시킬 수 있도록 한 반도체 소자의 절연막 평탄화방법에 관한 것이다.

Description

반도체 소자의 절연막 평탄화방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1 내지 제6도는 본 발명에 따른 반도체 소자의 절연막 평탄화 방법을 설명하기 위한 소자의 단면도.

Claims (1)

  1. 반도체 소자의 절연막 평탄화방법에 있어서, 단차가 높게 형성된 절연막상에 감광막을 도포하여 전체표면을 평탄화시키는 단계와, 상기 단계로부터 낮은 부분의 상기 절연막상에 존재하는 감광막은 노광되지 않도록 낮은 노광에너지를 이용하여 상기 감광막을 전면노광시키는 단계와, 상기 단계로부터 노광된 부분의 감광막을 제거하는 단계와, 상기 단계로부터 낮은 부분의 절연막상에 잔류된 감광막을 식각방지층으로 이용하여 노출된 부분의 절연막을 상기 잔류된 감광막표면까지 식각하는 단계와, 상기 단계로부터 상기 잔류된 감광막을 제거하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 절연막 평탄화방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950016400A 1995-06-20 1995-06-20 반도체 소자의 절연막 평탄화방법 KR970003620A (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019950016400A KR970003620A (ko) 1995-06-20 1995-06-20 반도체 소자의 절연막 평탄화방법
TW085107438A TW312813B (en) 1995-06-20 1996-06-19 Planarization method of film layer in semiconductor device
US08/665,895 US5804514A (en) 1995-06-20 1996-06-19 Method of planarizing a film of a semiconductor device
CN96110421A CN1050693C (zh) 1995-06-20 1996-06-20 半导体器件薄膜的平面化方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950016400A KR970003620A (ko) 1995-06-20 1995-06-20 반도체 소자의 절연막 평탄화방법

Publications (1)

Publication Number Publication Date
KR970003620A true KR970003620A (ko) 1997-01-28

Family

ID=19417572

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950016400A KR970003620A (ko) 1995-06-20 1995-06-20 반도체 소자의 절연막 평탄화방법

Country Status (4)

Country Link
US (1) US5804514A (ko)
KR (1) KR970003620A (ko)
CN (1) CN1050693C (ko)
TW (1) TW312813B (ko)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6032923A (en) * 1998-01-08 2000-03-07 Xerox Corporation Fluid valves having cantilevered blocking films
US6010828A (en) * 1998-02-19 2000-01-04 Lucent Technologies Inc. Method of and device for planarizing a surface of a semiconductor wafer
US6660618B1 (en) * 1999-08-18 2003-12-09 Advanced Micro Devices, Inc. Reverse mask and oxide layer deposition for reduction of vertical capacitance variation in multi-layer metallization systems
US6559040B1 (en) * 1999-10-20 2003-05-06 Taiwan Semiconductor Manufacturing Company Process for polishing the top surface of a polysilicon gate
CN100459100C (zh) * 2006-09-30 2009-02-04 中芯国际集成电路制造(上海)有限公司 平坦化方法及顶层金属层隔离结构的形成方法
CN102303953A (zh) * 2011-05-19 2012-01-04 华映视讯（吴江）有限公司 一种减少报废的基板蚀刻方法
CN111430231A (zh) * 2020-05-21 2020-07-17 中国科学院微电子研究所 一种平坦化方法及半导体器件

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1169022A (en) * 1982-04-19 1984-06-12 Kevin Duncan Integrated circuit planarizing process
US4952274A (en) * 1988-05-27 1990-08-28 Northern Telecom Limited Method for planarizing an insulating layer
US5245213A (en) * 1991-10-10 1993-09-14 Sgs-Thomson Microelectronics, Inc. Planarized semiconductor product

Also Published As

Publication number Publication date
CN1148264A (zh) 1997-04-23
US5804514A (en) 1998-09-08
TW312813B (en) 1997-08-11
CN1050693C (zh) 2000-03-22

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