CN1148264A - 半导体器件薄膜的平面化方法 - Google Patents

半导体器件薄膜的平面化方法 Download PDF

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CN1148264A
CN1148264A CN96110421A CN96110421A CN1148264A CN 1148264 A CN1148264 A CN 1148264A CN 96110421 A CN96110421 A CN 96110421A CN 96110421 A CN96110421 A CN 96110421A CN 1148264 A CN1148264 A CN 1148264A
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photoresist
film
dielectric film
semiconductor device
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CN1050693C (zh
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权炳仁
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SK Hynix Inc
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Hyundai Electronics Industries Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H01L21/31056—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/42—Stripping or agents therefor

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

本发明涉及一种半导体器件薄膜平面化方法，它通过改善平面化的方法可以提高器件的产量，该方法是在具有高拓扑结构的绝缘膜上涂敷光致抗蚀剂，用低能量曝光，在显影处理过程中保留处在绝缘膜凹陷部分的光致抗蚀剂，然后利用保留的光致抗蚀剂作为蚀刻阻挡层蚀刻暴露的绝缘膜。

Description

半导体器件薄膜的平面化方法
本发明涉及半导体器件薄膜的平面化方法，特别涉及半导体器件绝缘膜的平面化方法，它可以通过改善平面化方法提高器件的成品率，该方法是在具有高拓扑结构的绝缘膜上涂敷光致抗蚀剂，利用低能量完全曝光，在显影过程中保留处在绝缘膜凹陷部分的光致抗蚀剂，然后利用保留的光致抗蚀剂作为蚀刻阻挡层蚀刻暴露的绝缘膜。
在半导体器件的生产过程中，导电层一般形成在双层或多层结构中。因此，导电层之间的绝缘和平面化是必要的。这是通过形成绝缘膜来实现的。由于半导体器件集成度提高，底层较高的拓扑结构使得绝缘膜的拓扑结构相应变高。在导电层形成在具有较高拓扑结构的绝缘膜上的情况下，导电层将会断路或连接不良，由此降低了器件的生产率。因此，器件的平面化是非常重要的。现在阐明绝缘膜平面化的常规方法。
用在半导体器件制造过程中的绝缘膜平面化方法的现有技术是利用淀积BPSG(硼磷硅酸盐玻璃)然后使之流动，或者连续地形成绝缘膜和光致抗蚀剂，然后蚀刻，前者由于流动处理的限制平面化状态不良，后者由于用于光致抗蚀剂蚀刻的时间而需要许多处理时间，因此使得控制光致抗蚀剂和绝缘膜之间的蚀刻选择率非常困难，并出现不良的平面化状态。
因此，本发明的目的是提供一种半导体器件绝缘膜平面化的方法，它可以克服上述问题，这样的方法是在具有高拓扑结构的绝缘膜上涂敷光致抗蚀剂，使用低能量使其完全曝光，在显影过程中保留处在绝缘膜凹陷部分的光致抗蚀剂，然后利用保留的光致抗蚀剂作为蚀刻阻挡层蚀刻暴露的绝缘膜。
为了达到上述目的，半导体薄膜的平面化方法包括以下步骤：在具有高拓扑结构的薄膜上涂敷光致抗蚀剂，从而平面化该膜；除去部分光致抗蚀剂以保留涂敷在该膜凹陷部分上的光致抗蚀剂，由此暴露该膜的峰顶部分；除去该膜的峰顶部分；除去涂敷在该膜凹陷部分的光致抗蚀剂。
为了更加全面地理解本发明的目的和特征，应该结合附图了解以下的详细说明，其中：
图1～图6是阐明本发明的半导体器件绝缘膜平面化方法的剖视图。
在各附图中的相同的标号对应于相同部分。
下面将参照附图详细描述本发明。
图1～图6是阐明本发明的半导体器件绝缘膜平面化方法的剖视图。
图1表示器件的剖视图，其中在晶片1上形成绝缘膜2，其中由于底层的高拓扑结构使平面化状态不良。
图2表示器件的剖视图，其中在具有高拓扑结构的绝缘膜2上涂敷光致抗蚀剂3，以平面化全部表面。如果光致抗蚀剂具有低粘滞度，由于光致抗蚀剂的厚度在绝缘膜2峰顶部分上可较稀薄，绝缘膜的峰顶部可能由具有低能量的光源曝光。
图3表示器件的剖视图，其中由低能量的光源将光致抗蚀剂3全部曝光，绝缘膜2凹陷部分上的光致抗蚀剂未曝光。由此将光致抗蚀剂3分成曝光部分3B和非曝光部分3A。
图4表示器件的剖视图，其中在显影处理中除去曝光部分3B，其中绝缘膜2峰顶部分被暴露，绝缘膜的凹陷部被保留的光致抗蚀剂所覆盖。
图5表示器件的剖视图，其中通过利用非曝光部分3A作为蚀刻阻挡层来蚀刻绝缘膜2的暴露部分到要求的深度(在这种情况下，直到光致抗蚀剂3的非曝光部分的表面)使表面平面化。
图6表示器件的剖视图，其中除去非曝光部分3A以完成绝缘膜2的平面化。从图4的状态中，如图6的平面化可以通过控制光致抗蚀剂和绝缘膜之间的蚀刻选择性，然后同时蚀刻较高的绝缘膜和光致抗蚀剂的非曝光部分来获得。
如上所述，本发明具有利用下述方法可以提高器件成品率的突出效果，该方法包括：在具有高拓扑结构的绝缘膜上涂敷光致抗蚀剂来提高平面化，并以低能量全部曝光，在显影处理中保留绝缘膜凹陷部分的光致抗蚀剂，然后利用保留的光致抗蚀剂作为蚀刻阻挡层蚀刻暴露的绝缘膜。
虽然本发明公开的仅仅是绝缘膜的平面化方法，同样的方法也适用于平面化半导体器件中除绝缘膜以外的其它薄膜，如多晶硅膜，金属膜或硅化物膜。
虽然上述描述对优选实施例作了一定程度的说明，但这仅仅是对本发明原理的阐述。应该理解到本发明不限于这里所公开和阐述的实施例。因此，在本发明的精神和范围内可以作的所有变化皆包含在本发明进一步的实施例中。

Claims (6)

1.一种半导体薄膜平面化的方法，包括以下步骤：
在具有拓扑结构的薄膜上涂敷光致抗蚀剂；
除去部分所述光致抗蚀剂，保留在所述薄膜凹陷部分上的所述光致抗蚀剂，由此暴露所述薄膜的峰顶部分；
除去所述薄膜的所述峰顶部分；
除去涂敷在所述薄膜凹槽部分上的所述光致抗蚀剂。
2.根据权利要求1所述的方法，其特征在于：上述除去部分所述光致抗蚀剂的步骤包括：
使除所述光致抗蚀剂较低部分之外的所述光致抗蚀剂曝光；
除去所述光致抗蚀剂的曝光部分。
3.根据权利要求1所述的方法，其特征在于：把涂敷在所述薄膜凹陷部分上的所述光致抗蚀剂在上述除去所述薄膜峰顶部分步骤过程中用作掩模。
4.根据权利要求1所述的方法，其特征在于：所述薄膜为绝缘层。
5.根据权利要求1所述的方法，其特征在于：所述薄膜为多晶硅层。
6.根据权利要求1所述的方法，其特征在于：所述薄膜为金属层和硅化物层的任意一种。
CN96110421A 1995-06-20 1996-06-20 半导体器件薄膜的平面化方法 Expired - Fee Related CN1050693C (zh)

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KR1019950016400A KR970003620A (ko) 1995-06-20 1995-06-20 반도체 소자의 절연막 평탄화방법

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102303953A (zh) * 2011-05-19 2012-01-04 华映视讯（吴江）有限公司 一种减少报废的基板蚀刻方法
CN111430231A (zh) * 2020-05-21 2020-07-17 中国科学院微电子研究所 一种平坦化方法及半导体器件

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6032923A (en) * 1998-01-08 2000-03-07 Xerox Corporation Fluid valves having cantilevered blocking films
US6010828A (en) * 1998-02-19 2000-01-04 Lucent Technologies Inc. Method of and device for planarizing a surface of a semiconductor wafer
US6660618B1 (en) * 1999-08-18 2003-12-09 Advanced Micro Devices, Inc. Reverse mask and oxide layer deposition for reduction of vertical capacitance variation in multi-layer metallization systems
US6559040B1 (en) * 1999-10-20 2003-05-06 Taiwan Semiconductor Manufacturing Company Process for polishing the top surface of a polysilicon gate
CN100459100C (zh) * 2006-09-30 2009-02-04 中芯国际集成电路制造(上海)有限公司 平坦化方法及顶层金属层隔离结构的形成方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1169022A (en) * 1982-04-19 1984-06-12 Kevin Duncan Integrated circuit planarizing process
US4952274A (en) * 1988-05-27 1990-08-28 Northern Telecom Limited Method for planarizing an insulating layer
US5245213A (en) * 1991-10-10 1993-09-14 Sgs-Thomson Microelectronics, Inc. Planarized semiconductor product

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102303953A (zh) * 2011-05-19 2012-01-04 华映视讯（吴江）有限公司 一种减少报废的基板蚀刻方法
CN111430231A (zh) * 2020-05-21 2020-07-17 中国科学院微电子研究所 一种平坦化方法及半导体器件

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US5804514A (en) 1998-09-08
CN1050693C (zh) 2000-03-22
KR970003620A (ko) 1997-01-28

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