KR960043025A - 평탄화방법 - Google Patents

평탄화방법 Download PDF

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Publication number
KR960043025A
KR960043025A KR1019950014438A KR19950014438A KR960043025A KR 960043025 A KR960043025 A KR 960043025A KR 1019950014438 A KR1019950014438 A KR 1019950014438A KR 19950014438 A KR19950014438 A KR 19950014438A KR 960043025 A KR960043025 A KR 960043025A
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KR
South Korea
Prior art keywords
photosensitive layer
layer
conductive pattern
insulating layer
photosensitive
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Application number
KR1019950014438A
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English (en)
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KR0153980B1 (ko
Inventor
노재우
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배순훈
대우전자 주식회사
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Priority to KR1019950014438A priority Critical patent/KR0153980B1/ko
Publication of KR960043025A publication Critical patent/KR960043025A/ko
Application granted granted Critical
Publication of KR0153980B1 publication Critical patent/KR0153980B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 평탄화 방법에 관한 것으로서, 반도체기판 상부의 소정 부분에 도선 패턴을 형성하고, 이 도선 패턴에 제1감광층과 오버 행된 제2감광층을 두께의 합이 도선 패턴의 두께보다 2배정도가 되도록 형성한 후 절연층을 도선 패턴과 동일한 두께로 스퍼터링 또는 진공증착하여 제2감광층의 오버 행된 부분에 의해 제1감광층과 접촉되지 않게 형성하고 제1 및 제2감광층을 제거함과 동시에 이 제2감광층의 상부에 형성된 절연층을 제거하여 도선패턴과 절연층의 표면이 평탄해지도록 한다. 따라서, 도선 패턴 사이의 절연층을 도선 패턴과 동일한 두께로 형성하여 단차를 완전히 제거함으로 평탄화를 이룰 수 있다.

Description

평탄화방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도(A) 내지 (D)는 본 발명에 따른 평탄화 방법의 순서도.

Claims (5)

  1. 반도체기판(21)의 상부에 소정의 도선 패턴(23)을 형성하는 공정과, 상기 도선 패턴(23)이 형성된 반도체기판(21)의 상부에 제1감광층(25)과 이 제1감광층(25)에 오버 행된 제2감광층(27)을 형성하는 공정과, 상기 반도체기판(21)의 상기 도선 패턴(23)이 형성되지 않아 노출된 부분과 상기 제2감광층(27)의 상부에 절연층(29)을 상기 제1감광층(25)의 측면과 접촉되지 않게 형성하는 공정과, 상기 제1 및 제2감광층(25)(27)을 제거함과 동시에 상기 제2감광층(27)에 형성된 절연층(29)을 제거하는 공정을 구비하는 평탄화방법.
  2. 제1항에 있어서, 상기 제1감광층(25)의 표면을 모노 클로로벤젠과 반응시켜 상기 제2감광층(27)을 형성하는 평탄화방법.
  3. 제1항에 있어서, 상기 제1 및 제2감광층(25)(27) 두께의 합이 도선 패턴(23) 두께의 2배가 되도록 형성하는 평탄화방법.
  4. 제1항에 있어서, 상기 절연층(29)을 SiO2또는 Si3Ni4로 형성하는 평탄화방법.
  5. 제4항에 있어서, 상기 절연층(29)을 스퍼터링 또는 진공증착하여 형성하는 평탄화방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950014438A 1995-05-31 1995-05-31 평탄화방법 KR0153980B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950014438A KR0153980B1 (ko) 1995-05-31 1995-05-31 평탄화방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950014438A KR0153980B1 (ko) 1995-05-31 1995-05-31 평탄화방법

Publications (2)

Publication Number Publication Date
KR960043025A true KR960043025A (ko) 1996-12-21
KR0153980B1 KR0153980B1 (ko) 1998-12-01

Family

ID=19416320

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950014438A KR0153980B1 (ko) 1995-05-31 1995-05-31 평탄화방법

Country Status (1)

Country Link
KR (1) KR0153980B1 (ko)

Also Published As

Publication number Publication date
KR0153980B1 (ko) 1998-12-01

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