KR960042975A - 접속 홀 형성 방법 - Google Patents

접속 홀 형성 방법 Download PDF

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KR960042975A
KR960042975A KR1019960018305A KR19960018305A KR960042975A KR 960042975 A KR960042975 A KR 960042975A KR 1019960018305 A KR1019960018305 A KR 1019960018305A KR 19960018305 A KR19960018305 A KR 19960018305A KR 960042975 A KR960042975 A KR 960042975A
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film
insulating film
etching
connection hole
pattern
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데쯔지 나가야마
마사끼 미나미
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이데이 노부유끼
소니 가부시끼가이샤
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
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    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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Abstract

접속 홀 형성 방법에 있어서, 상기 방법은 SiN을 기초로 한 재료로 이루어진 에칭 정지막과, SiOx를 기초로 한 재료로 이루어진 층간 절연막을 순서에 따라 기판 상에 도포하는 단계; 접속 홀 패턴에 근거하여 층간 절연막 상에 유기막 패턴을 형성하는 단계; 에칭 정지막에 대해 선택비를 유지하면서 유기막 패턴을 마스크로 사용하여 층간 절연막을 건식 에칭하는 단계; 산소를 기초로 한 화학 종류를 함유하는 에칭 반응계를 사용하여, 건식 에칭으로서 에칭 정지막의 노출된 표면 상에 증착된 탄소를 기초로 한 보호막을 제거하는 단계; 및 에칭 정지막을 선택적으로 에칭함으로써 접속 홀을 완성하는 단계를 구비한다.

Description

접속 홀 형성 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 레지스트 패턴이 완성된 상태를 상세히 도시하는 것으로, SAC 공정에 근거하여 SRAM의 비트 라인 접촉부를 형성하는 데 본 발명이 적용되는 예의 전형적인 단면도.

Claims (12)

  1. 접속 홀 형성 방법에 있어서, SiN을 기초로 한 재료로 이루어진 에칭 정지막(an etching stopper film)과 SiOx를 기초로 한 재료로 이루어진 층간 절연막(an interlayer insulating film)을 순서에 따라 기판 상에 도포하는 제1단계; 접속 홀 패턴에 근거하여 상기 층간 절연막 상에 유기막 패턴을 형성하는 제2단계; 상기 에칭 정지막에 대한 선택비를 유지하면서 상기 유기막 패턴을 마스크로 사용하여 층간 절연막을 건식 에칭하는 제3단계; 산소를 기초로 한 화학 종류를 함유하는 에칭 반응계를 사용하여, 상기 건식 에칭에 의해 상기 에칭 정지막의 노출된 표면 상에 증착된 탄소를 기초로 한 보호막을 제거하는 제4단계; 및 상기 에칭 정지막을 선택적으로 에칭함으로써 접속 홀을 완성하는 제5단계를 구비하는 것을 특징으로 하는 접속 홀 형성 방법.
  2. 제1항에 있어서, 상기 제4단계에서 탄소를 기초로 한 보호막의 제거는 산소를 기초로 한 화학 종류로 주로 이루어진 활성 종류의 플라즈마를 사용하여 수행되는 것을 특징으로 하는 접속 홀 형성 방법.
  3. 제2항에 있어서, 상기 플라즈마는 적어도 O2를 함유하는 가스를 방전시킴으로써 여기되는 것을 특징으로 하는 접속 홀 형성 방법.
  4. 제2항에 있어서, 상기 전체 유기막 패턴은 상기 제4단계에서 상기 탄소를 기초로 한 보호막과 함께 제거되는 것을 특징으로 하는 접속 홀 형성 방법.
  5. 제2항에 있어서, 상기 제3단계에서 상기 제5단계까지 일련의 단계들중 적어도 연속하는 두 단계는 동일한 플라즈마 챔버에 상기 기판이 유지되어 있는 상태에서 수행되는 것을 특징으로 하는 접속 홀 형성 방법.
  6. 제2항에 있어서, 상기 제3단계에서 상기 층간 절연막에 대한 건식 에칭은 플라즈마 챔버에 단일 전극형 정전 청크(a single electrode type electrostatic chunk)를 갖는 기판 스테이지 상에 장착되어 있는 상태에서 수행되고, 상기 제4단계에서 상기 탄소를 기초로 한 보호막의 제거는 상기 단일 전극형 정전 청크의 잔류하는 전하들을 제거하기 위한 플라즈마 방전으로서의 역할을 하는 방법으로 수행되는 것을 특징으로 하는 접속 홀 형성 방법.
  7. 제1항에 있어서, SiOx를 기초로 한 재료로 각각 이루어진 오프셋 절연막(an offset insulating film)과 측벽 절연막으로 각각 덮여 있는 상부면과 측면들을 갖는 전극 패턴이 상기 기판 상에 미리 형성되고, 상기 접속 홀은 그 일부 바닥 표면이 적어도 상기 측벽 절연막을 덮도록 개방되어 있는 것을 특징으로 하는 접속 홀 형성 방법.
  8. 접속 홀 형성 방법에 있어서, SiN을 기초로 한 재료로 이루어진 에칭 정지막과 SiOx를 기초로 한 재료로 이루어진 층간 절연막을 순서에 따라 기판 상에 도포하는 제1단계; 접속 홀 패턴에 근거하여 상기 층간 절연막 상에 유기막 패턴을 형성하는 제2단계; 상기 에칭 정지막에 대한 선택비를 유지하면서 상기 유기막 패턴을 마스크로 사용하여 상기 층간 절연막을 건식 에칭하는 제3단계; 및 적어도 산소를 기초로 한 화학 종류를 함유하는 에칭 반응계를 사용하여 상기 건식 에칭에 의해 상기 에칭 정지막의 노출된 표면 상에 증착된 탄소를 기초로 한 보호막과, 상기 에칭 정지막 모두를 동시에 제거하는 제4단계를 구비하는 것을 특징으로 하는 접속 홀 형성 방법.
  9. 제8항에 있어서, 상기 제4단계에서 상기 탄소를 기초로 한 보호막과 상기 에칭 정지막의 동시 제거는 산소를 기초로 한 화학 종류와 SiN을 기초로 한 에칭 종류를 동시에 발생할 수 있는 플라즈마를 사용하여 수행되는 것을 특징으로 하는 접속 홀 형성 방법.
  10. 제9항에 있어서, 상기 플라즈마는 적어도 탄화 플루오르를 기초로 한 화합물과 O2를 함유하는 가스를 방전시킴으로써 여기되는 것을 특징으로 하는 접속 홀 형성 방법.
  11. 제8항에 있어서, 상기 제3단계에서 상기 제4단계는 상기 기판이 동일한 플라즈마 챔버에 유지되어 있는 상태에서 수행되는 것을 특징으로 하는 접속 홀 형성 방법.
  12. 제8항에 있어서, SiOx를 기초로 한 재료로 각각 이루어진 오프셋 절연막(an offset insulating film)과 측벽 절연막(a side wall insulating film)으로 각각 덮여 있는 상부 면과 측면들을 갖는 전극 패턴이 상기 기판상에 형성되고, 상기 접속 홀은 그 일부 바닥 표면이 적어도 상기 측벽 절연막을 덮도록 개방되어 있는 것을 특징으로 하는 접속 홀 형성 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960018305A 1995-05-29 1996-05-28 접속 홀 형성 방법 KR960042975A (ko)

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JP2959996A JPH0950986A (ja) 1995-05-29 1996-02-16 接続孔の形成方法

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