KR950027956A - 반도체 소자의 콘택홀 형성방법 - Google Patents

반도체 소자의 콘택홀 형성방법 Download PDF

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KR950027956A
KR950027956A KR1019940005627A KR19940005627A KR950027956A KR 950027956 A KR950027956 A KR 950027956A KR 1019940005627 A KR1019940005627 A KR 1019940005627A KR 19940005627 A KR19940005627 A KR 19940005627A KR 950027956 A KR950027956 A KR 950027956A
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South Korea
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contact hole
forming
semiconductor substrate
planarization layer
silicon oxide
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KR1019940005627A
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English (en)
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KR0126646B1 (ko
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이헌철
손곤
박해성
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김주용
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 반도체소자의 콘택홀 형성방법에 관한 것으로, 반도체기판 상부에 워드라인을 형성하고, 그 상부에 절연막, 그측벽에 절연막 스페이서를 형성하고 전체구조상부에 실리콘산화막을 일정두께 증착하고, 그상부에 평탄화층을 형성하고, 그 상부에 콘택마스크를 형성한 다음, C4F8과 CO가스를 사용하고 고밀도의 플라즈마 반응용기를 이용하여 콘택홀 식각공정을 실시하되 형성하려는 콘택홀의 측벽에는 폴리머가 상기 반도체기판에 가까워질수록 두꺼워지도록하여 미세콘택홀을 형성할 수 있는 슬로프 식각을 실시함으로써 상기 평탄화층과 실리콘산화막을 식각하여 콘택홀을 형성한 다음, 산소플라즈마 식각공정으로 상기 콘택마스크와 폴리머를 제거함으로써, 종래에 복잡한 자기정렬적 콘택홀을 형성방법보다 더 간단하게 더 미세한 콘택홀을 형성할 수 있어 반도체소자를 고집적화시키고 콘택홀 형성공정과 공정시간을 단축시켜 생산성을 향상시키고 단가를 절감시킬 수 있는 기술이다.

Description

반도체 소자의 콘택홀 형성방법.
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2A도 내지 제2C도는 본 발명에 의한 반도체소자의 콘택홀 형성공정을 도시한 단면도.

Claims (5)

  1. 반도체소자의 콘택홀 형성방법에 있어서, 반도체기판 상부에 워드라인을 형성하고 상기 워드라인의 상부에 실리콘산화막을 사용하여 절연막을 형성한 다음, 상기 워드라인의 측벽에 산화막을 사용하여 스페이서를 형성하는 공정과, 상부구조전체에 절연막인 실리콘산화막을 일정두께 증착하는 공정과, 상기 실리콘산화막의 상부에 BPSG를 사용하여 평탄화층을 형성하는 공정과, 상기 평탄화층의 상부에 감광막을 이용하여 콘택마스크를 형성하는 공정과, 상기 평탄화층과 실리콘산화막을 식각하되 전체구조상부로부터 C4F8과 CO가스를 사용하여 콘택홀의 측벽에 많은 폴리머가 발생되도록 슬로프 식각을 하여 상기 콘택마스크 보다 미세한 콘택홀을 형성하는 공정과, 산소플라즈마 식각공정으로 상기 콘택마스크와 폴리머를 식각하는 공정을 포함하는 반도체소자의 콘택홀 형성방법.
  2. 제1항에 있어서, 상기 C4F8은 대신에 C4F8를 사용하는 것을 특징으로하는 반도체 소자의 콘택홀 형성방법.
  3. 제1항에 있어서, 상기 C4F8의 플로우 비율은 1SCCM 이상에서 200SCCM이하로 하는 것을 특징으로하는 반도체소자의 콘택홀 형성방법.
  4. 제1항에 있어서, 상기 CO가스의 플로우 비율은 1SCCM 이상에서 200SCCM이하로 하는 것을 특징으로하는 반도체소자의 콘택홀 형성방법.
  5. 제1항에 있어서, 상기 C4F8과 CO가스를 이용한 상기 콘택홀 식각공정은 높은 밀도의 플라즈마 반응용기를 이용하여 실시하는 것을 특징으로 하는 반도체소자의 콘택홀 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940005627A 1994-03-21 1994-03-21 반도체소자의 콘택홀 형성방법 KR0126646B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940005627A KR0126646B1 (ko) 1994-03-21 1994-03-21 반도체소자의 콘택홀 형성방법

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KR1019940005627A KR0126646B1 (ko) 1994-03-21 1994-03-21 반도체소자의 콘택홀 형성방법

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KR0126646B1 KR0126646B1 (ko) 1998-04-02

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990075068A (ko) * 1998-03-17 1999-10-05 윤종용 절연막 식각방법 및 이를 이용한 반도체장치 제조방법
KR20030096671A (ko) * 2002-06-17 2003-12-31 동부전자 주식회사 반도체 소자의 콘택홀 형성 방법
KR101115526B1 (ko) * 2010-01-25 2012-02-27 전자부품연구원 관통 실리콘 비아 제조 방법

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100510067B1 (ko) * 1999-12-30 2005-08-26 주식회사 하이닉스반도체 반도체 소자 제조를 위한 자기정렬콘택 식각 방법

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990075068A (ko) * 1998-03-17 1999-10-05 윤종용 절연막 식각방법 및 이를 이용한 반도체장치 제조방법
KR20030096671A (ko) * 2002-06-17 2003-12-31 동부전자 주식회사 반도체 소자의 콘택홀 형성 방법
KR101115526B1 (ko) * 2010-01-25 2012-02-27 전자부품연구원 관통 실리콘 비아 제조 방법

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