KR960035794A - 엔모스(nmos) 집적회로장치에서 서브문턱전류를 감소시키는 큰 경사각도 붕소 이온주입 방법 - Google Patents

엔모스(nmos) 집적회로장치에서 서브문턱전류를 감소시키는 큰 경사각도 붕소 이온주입 방법 Download PDF

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KR960035794A
KR960035794A KR1019960006076A KR19960006076A KR960035794A KR 960035794 A KR960035794 A KR 960035794A KR 1019960006076 A KR1019960006076 A KR 1019960006076A KR 19960006076 A KR19960006076 A KR 19960006076A KR 960035794 A KR960035794 A KR 960035794A
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semiconductor substrate
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ion implantation
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안줌 모하메드
에치. 쿠프 클라우스
에치. 카이오 마웅
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미키오 이시마루
어드밴스드 마이크로 디바이시즈, 인코포레이티드
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Abstract

큰 타일 각도 이온주입의 반도체 구조는 채널 에지에서 문턱시프트 혹은 롤오프를 줄이기 위해 제공된다. 문턱 스프트를 최고화함에 의해, 기판표면 또는 근처에서 숏 채널 효과와 서브문턱 전류는 줄어든다. 반도체 구조는 필드에리어와, 소스/드레인사이의 접합 뿐만아니라 채널 및 소스/드레인사이의 접합으로 수직하지 않게 붕소를 이온주입함에 의해 만들어진다. 이러한 임계영역으로의 붕소배치는 공정 온도 사이클로부터 기인하는 문턱전압 조절 이온주입 종류와 채널 스톱 이온주입 종류의 격리와 재배치를 리플레니싱하게 한다. 가벼운 붕소 이온을 사용하는 것을 어닐링 온도의 감소를 허용하고, 따라서 고온 어닐링에 의해 야기되는 증대된 재배치 및 확산의 단점을 배제한다.

Description

엔모스(NMOS) 집적회로장치에서 서브문턱전류를 감소시키는 큰 경사각도 붕소 이온주입 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제6도는 본 발명에 의한 프로세스 단계에 따라 형성된 반도체장치를 보여주는 제1도의 A-A평면을 따른 단면도.

Claims (15)

  1. 반도체 기판 상부 표면의 활성영역에 오프닝을 제공하는 단계와 : 상기 반도체 기판 상부 표면에 실질적으로 수직인 각도로 상기 오프닝을 통해 상기 활성영역으로 붕소 이온을 이온주입하는 단계와 : 상기 활성역의 부분에 다결정실리콘 트레이스 엘리먼트를 패턴하는 단계와 : 상기 반도체 기판 상부 표면에 대해 수직하지 않은 각도로 상기 오프닝을 통해 상기 활성영역으로 붕소 이온을 이온주입하는 단계를 포함함을 특징으로 하는 집적회로 제작 방법.
  2. 제1항에 있어서, 상기 제1이온주입단계는 붕소이온을 상기 반도체 기판 상부표면 아래의 제1깊이에 농도분포가 최고인 점으로 주입하는 단계를 포함하고, 상기 제2이온주입단계는 상기 반도체 기판 상부표면 아래의 제2깊이에 농도분포가 최고인 점으로 붕소를 주입하는 단계를 포함함을 특징으로 하는 집적회로 제작방법.
  3. 제2항에 있어서, 상기 제1깊이는 상기 제2깊이보다 큰 것을 특징으로 하는 직접회로 제작방법.
  4. 제1항에 있어서, 상기 제2이온주입단계는 상기 다결정실리콘 아래의 상기 활성영역으로 상기 붕소 이온의 세트를 주입하는 단계를 포함함을 특징으로 하는 직접회로 제작방법.
  5. 제1항에 있어서, 상기 제2이온주입단계 다음으로, 상기 활성영역에 n-타입 이온을 주입하는 단계를 포함함을 특징으로 하는 직접회로 제작방법.
  6. 제5항에 있어서, 상기 n-타입 이온은 붕소보다 원자질량이 큰 것임을 특징으로 하는 집적회로 제작방법.
  7. 제5항에 있어서, 상기 n-타입 이온은 비소임을 특징으로 하는 집적회로 제작방법.
  8. 제1항에 있어서, 상기 오프닝을 제공하는 단계는 상기 반도체 기판 상부 표면에 패드 옥사이드를 성장시키는 단계와, 상기 패트 옥사이드에 실리콘 질화물을 적충시키는 단계와, 상기 반도체 기판 상부 표면의 필드 영역을 노출시키도록 상기 실리콘 질화물과 상기 패드옥사이드의 부분을 선택적으로 제거하는 단계와, 상기 반도체 기판 상부 표면의 노출된 필드영역에 인슐레이션 물질을 형성하는 단계와, 인슐레이션 물질을 통해 상기 오프닝을 형성하기 위해 상기 활성영역에 포개어진 상기 패드 옥사이드와 상기 실리콘 질화물이 남겨진 것을 제거하는 단계를 포함함을 특징으로 하는 직접회로 제작방법.
  9. 제8항에 있어서, 상기 제2이온주입단계는 상기 인슐레이션 물질 아래의 상기 반도체 기판 상부 표면으로 상기 붕소이온은 세트를 주입하는 단계를 포함함을 특징으로 하는 직접회로 제작방법.
  10. 제1항의 방법에 의해 제작된 직접회로.
  11. 패턴이 형성된 인슐레이션 물질아래에 존재하는 반도체 기판의 부분인 필드영역으로 붕소를 제공하는 단계와 : 패턴이 형성된 다결정실리콘 트레이스 엘리먼트 아래의 상기 기판내에 존재하고 상기 필드 영역으로부터 측방향으로 이격된 채널영역으로 붕소를 제공하는 단계와 : 상기 채널영역 및 상기 필드 영역내에서 농도분포가 최고인 제1점에 상기 이온주입된 붕소 이온의 세트가 존재하는 상기 반도체 기판에 대해 수직이 아닌 각도로 상기 채널영역의 부분에 붕소 이온을 이온주입하는 단계와 : 상기 농도분포가 최고인 제2점에서 상기 이온주입된 비소이온이 존재하고, 상기 필드영역 및 상기 채널영역 사이에 소스 및 드레인영역이 존재하는 소스 및 드레인 영역으로 비소 이온을 이온주입하는 단계를 포함함을 특징으로 하는 드레인 유도 베리어의 저-유도전류를 감소시키기 위해 인접한 소스 및 드레인영역에 채널영역 및 필드영역에서부터 붕소의 확산 및 격리를 리플레니싱하기 위한 방법.
  12. 제11항에 있어서, 상기 농도분포가 최고인 제1점은 상기 농도분포가 최고인 제2점보다 상기 반도체 기판의 상부포면에 관하며 더 얕게 됨을 특징으로 하는 드레인 유도 베리어 저-유도전류를 감소시키기 위해 인접한 소스 및 드레인영역에 채널영역 및 필드영역에서 부터 붕소 확산 및 격리를 리플레니싱하기 위한 방법.
  13. 제11항에 있어서, 상기 수직이 아닌 각도는 상기 반도체 기판의 상부표면에 대해 예각임을 특징으로 하는 드레인 유도 베리어의 저-유도전류를 감소시키기 위해 인접한 소스 및 드레인영역에 채널영역 및 필드영역에서부터 비소의 확산 및 격리를 리플레니싱하기 위한 방법.
  14. 제11항에 있어서, 상기 인슐레이션 물질은 실리콘 디옥사이드를 포함함을 특징으로 하는 드레인 유도 베리어의 저-유도전류를 감소시키기 위해 인접한 소스 및 드레인영역에 채널영역 및 필드영역에서부터 붕소의 확산 및 격리를 리플레니싱하기 위한 방법.
  15. 제11항의 방법에 의해 제조된 직접회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960006076A 1995-03-08 1996-03-08 엔모스집적회로장치에서서브문턱전류를감소시키는큰경사각도붕소이온주입방법 KR100379640B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/400,609 US5593907A (en) 1995-03-08 1995-03-08 Large tilt angle boron implant methodology for reducing subthreshold current in NMOS integrated circuit devices
US08/400609 1995-03-08

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Families Citing this family (67)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5851886A (en) * 1995-10-23 1998-12-22 Advanced Micro Devices, Inc. Method of large angle tilt implant of channel region
US5821147A (en) * 1995-12-11 1998-10-13 Lucent Technologies, Inc. Integrated circuit fabrication
EP0817247A1 (en) * 1996-06-26 1998-01-07 STMicroelectronics S.r.l. Process for the fabrication of integrated circuits with contacts self-aligned to active areas
US6417550B1 (en) * 1996-08-30 2002-07-09 Altera Corporation High voltage MOS devices with high gated-diode breakdown voltage and punch-through voltage
US5985724A (en) * 1996-10-01 1999-11-16 Advanced Micro Devices, Inc. Method for forming asymmetrical p-channel transistor having nitrided oxide patterned to selectively form a sidewall spacer
US6020244A (en) * 1996-12-30 2000-02-01 Intel Corporation Channel dopant implantation with automatic compensation for variations in critical dimension
CN1199926A (zh) 1997-05-21 1998-11-25 日本电气株式会社 一种半导体器件的制造方法
US6483157B1 (en) * 1997-06-20 2002-11-19 Advanced Micro Devices, Inc. Asymmetrical transistor having a barrier-incorporated gate oxide and a graded implant only in the drain-side junction area
TW370719B (en) * 1997-10-23 1999-09-21 Winbond Electronics Corp Manufacturing method of anti-electrostatic discharge element
US5970353A (en) * 1998-03-30 1999-10-19 Advanced Micro Devices, Inc. Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion
US6008099A (en) * 1998-03-30 1999-12-28 Advanced Micro Devices, Inc. Fabrication process employing a single dopant implant for formation of a drain extension region and a drain region of an LDD MOSFET using enhanced lateral diffusion
US6016067A (en) * 1998-04-06 2000-01-18 Intersil Corporation Sample-and-hold circuit having reduced amplifier offset effects and related methods
US6002277A (en) * 1998-04-06 1999-12-14 Intersil Corporation Sample-and-hold circuit having reduced parasitic diode effects and related methods
US6069502A (en) * 1998-04-06 2000-05-30 Intersil Corporation Sample-and-hold circuit having reduced subthreshold conduction effects and related methods
EP0957521A1 (en) 1998-05-11 1999-11-17 STMicroelectronics S.r.l. Matrix of memory cells fabricated by means of a self-aligned source process, comprising ROM memory cells, and related manufacturing process
US6274442B1 (en) 1998-07-15 2001-08-14 Advanced Micro Devices, Inc. Transistor having a nitrogen incorporated epitaxially grown gate dielectric and method of making same
JP3237626B2 (ja) 1998-10-02 2001-12-10 日本電気株式会社 半導体装置の製造方法
US6274887B1 (en) * 1998-11-02 2001-08-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method therefor
US6200869B1 (en) 1998-11-06 2001-03-13 Advanced Micro Devices, Inc. Method of fabricating an integrated circuit with ultra-shallow source/drain extensions
US6180476B1 (en) * 1998-11-06 2001-01-30 Advanced Micro Devices, Inc. Dual amorphization implant process for ultra-shallow drain and source extensions
US6225173B1 (en) 1998-11-06 2001-05-01 Advanced Micro Devices, Inc. Recessed channel structure for manufacturing shallow source/drain extensions
US6297115B1 (en) 1998-11-06 2001-10-02 Advanced Micro Devices, Inc. Cmos processs with low thermal budget
US7141821B1 (en) * 1998-11-10 2006-11-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having an impurity gradient in the impurity regions and method of manufacture
US6277679B1 (en) 1998-11-25 2001-08-21 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing thin film transistor
US6184112B1 (en) * 1998-12-02 2001-02-06 Advanced Micro Devices, Inc. Method of forming a MOSFET transistor with a shallow abrupt retrograde dopant profile
US6174778B1 (en) * 1998-12-15 2001-01-16 United Microelectronics Corp. Method of fabricating metal oxide semiconductor
US6265291B1 (en) 1999-01-04 2001-07-24 Advanced Micro Devices, Inc. Circuit fabrication method which optimizes source/drain contact resistance
US6184097B1 (en) * 1999-02-22 2001-02-06 Advanced Micro Devices, Inc. Process for forming ultra-shallow source/drain extensions
US6271132B1 (en) 1999-05-03 2001-08-07 Advanced Micro Devices, Inc. Self-aligned source and drain extensions fabricated in a damascene contact and gate process
US6291278B1 (en) 1999-05-03 2001-09-18 Advanced Micro Devices, Inc. Method of forming transistors with self aligned damascene gate contact
US6194748B1 (en) 1999-05-03 2001-02-27 Advanced Micro Devices, Inc. MOSFET with suppressed gate-edge fringing field effect
US6492249B2 (en) 1999-05-03 2002-12-10 Advanced Micro Devices, Inc. High-K gate dielectric process with process with self aligned damascene contact to damascene gate and a low-k inter level dielectric
US6265293B1 (en) 1999-08-27 2001-07-24 Advanced Micro Devices, Inc. CMOS transistors fabricated in optimized RTA scheme
US6403433B1 (en) 1999-09-16 2002-06-11 Advanced Micro Devices, Inc. Source/drain doping technique for ultra-thin-body SOI MOS transistors
US6646287B1 (en) 1999-11-19 2003-11-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device with tapered gate and insulating film
US6465315B1 (en) 2000-01-03 2002-10-15 Advanced Micro Devices, Inc. MOS transistor with local channel compensation implant
US7019363B1 (en) 2000-01-04 2006-03-28 Advanced Micro Devices, Inc. MOS transistor with asymmetrical source/drain extensions
US6333244B1 (en) 2000-01-26 2001-12-25 Advanced Micro Devices, Inc. CMOS fabrication process with differential rapid thermal anneal scheme
US6372589B1 (en) 2000-04-19 2002-04-16 Advanced Micro Devices, Inc. Method of forming ultra-shallow source/drain extension by impurity diffusion from doped dielectric spacer
US6420218B1 (en) 2000-04-24 2002-07-16 Advanced Micro Devices, Inc. Ultra-thin-body SOI MOS transistors having recessed source and drain regions
US6361874B1 (en) 2000-06-20 2002-03-26 Advanced Micro Devices, Inc. Dual amorphization process optimized to reduce gate line over-melt
US6368947B1 (en) 2000-06-20 2002-04-09 Advanced Micro Devices, Inc. Process utilizing a cap layer optimized to reduce gate line over-melt
US6399450B1 (en) 2000-07-05 2002-06-04 Advanced Micro Devices, Inc. Low thermal budget process for manufacturing MOS transistors having elevated source and drain regions
US6630386B1 (en) 2000-07-18 2003-10-07 Advanced Micro Devices, Inc CMOS manufacturing process with self-amorphized source/drain junctions and extensions
US6521502B1 (en) 2000-08-07 2003-02-18 Advanced Micro Devices, Inc. Solid phase epitaxy activation process for source/drain junction extensions and halo regions
US6472282B1 (en) 2000-08-15 2002-10-29 Advanced Micro Devices, Inc. Self-amorphized regions for transistors
US6727149B1 (en) * 2000-12-07 2004-04-27 Advanced Micro Devices, Inc. Method of making a hybrid SOI device that suppresses floating body effects
US6756277B1 (en) 2001-02-09 2004-06-29 Advanced Micro Devices, Inc. Replacement gate process for transistors having elevated source and drain regions
US6551885B1 (en) 2001-02-09 2003-04-22 Advanced Micro Devices, Inc. Low temperature process for a thin film transistor
US6787424B1 (en) 2001-02-09 2004-09-07 Advanced Micro Devices, Inc. Fully depleted SOI transistor with elevated source and drain
US6495437B1 (en) 2001-02-09 2002-12-17 Advanced Micro Devices, Inc. Low temperature process to locally form high-k gate dielectrics
US6403434B1 (en) 2001-02-09 2002-06-11 Advanced Micro Devices, Inc. Process for manufacturing MOS transistors having elevated source and drain regions and a high-k gate dielectric
US6617219B1 (en) 2001-02-15 2003-09-09 Advanced Micro Devices, Inc. Semiconductor device and method for lowering miller capacitance by modifying source/drain extensions for high speed microprocessors
US6743685B1 (en) * 2001-02-15 2004-06-01 Advanced Micro Devices, Inc. Semiconductor device and method for lowering miller capacitance for high-speed microprocessors
US6420776B1 (en) 2001-03-01 2002-07-16 Amkor Technology, Inc. Structure including electronic components singulated using laser cutting
US6509221B1 (en) 2001-11-15 2003-01-21 International Business Machines Corporation Method for forming high performance CMOS devices with elevated sidewall spacers
KR100434702B1 (ko) * 2001-12-27 2004-06-07 주식회사 하이닉스반도체 리플레쉬 특성을 향상시키기 위한 반도체 소자의 제조방법
US6506654B1 (en) * 2002-03-26 2003-01-14 Advanced Micro Devices, Inc. Source-side stacking fault body-tie for partially-depleted SOI MOSFET hysteresis control
US6905923B1 (en) 2003-07-15 2005-06-14 Advanced Micro Devices, Inc. Offset spacer process for forming N-type transistors
US6930007B2 (en) * 2003-09-15 2005-08-16 Texas Instruments Incorporated Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance
US7274076B2 (en) 2003-10-20 2007-09-25 Micron Technology, Inc. Threshold voltage adjustment for long channel transistors
KR101044609B1 (ko) 2003-12-01 2011-06-29 매그나칩 반도체 유한회사 반도체소자 및 그 형성방법
US7312125B1 (en) 2004-02-05 2007-12-25 Advanced Micro Devices, Inc. Fully depleted strained semiconductor on insulator transistor and method of making the same
US7678640B1 (en) 2005-06-28 2010-03-16 Cypress Semiconductor Corporation Method of threshold voltage control in metal-oxide-semiconductor devices
DE102008026213B3 (de) * 2008-05-30 2009-09-24 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Durchlassstromerhöhung in Transistoren durch asymmetrische Amorphisierungsimplantation
US8900954B2 (en) 2011-11-04 2014-12-02 International Business Machines Corporation Blanket short channel roll-up implant with non-angled long channel compensating implant through patterned opening
US9941377B2 (en) * 2015-12-29 2018-04-10 Qualcomm Incorporated Semiconductor devices with wider field gates for reduced gate resistance

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4599118A (en) * 1981-12-30 1986-07-08 Mostek Corporation Method of making MOSFET by multiple implantations followed by a diffusion step
US5218221A (en) * 1989-10-20 1993-06-08 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
US5158903A (en) * 1989-11-01 1992-10-27 Matsushita Electric Industrial Co., Ltd. Method for producing a field-effect type semiconductor device
KR940010930B1 (ko) * 1990-03-13 1994-11-19 가부시키가이샤 도시바 반도체장치의 제조방법
JP2633104B2 (ja) * 1991-05-21 1997-07-23 シャープ株式会社 半導体装置の製造方法
US5320974A (en) * 1991-07-25 1994-06-14 Matsushita Electric Industrial Co., Ltd. Method for making semiconductor transistor device by implanting punch through stoppers
JP2848757B2 (ja) * 1993-03-19 1999-01-20 シャープ株式会社 電界効果トランジスタおよびその製造方法
US5308780A (en) * 1993-07-22 1994-05-03 United Microelectronics Corporation Surface counter-doped N-LDD for high hot carrier reliability
US5360749A (en) * 1993-12-10 1994-11-01 Advanced Micro Devices, Inc. Method of making semiconductor structure with germanium implant for reducing short channel effects and subthreshold current near the substrate surface
US5393689A (en) * 1994-02-28 1995-02-28 Motorola, Inc. Process for forming a static-random-access memory cell
US5409848A (en) * 1994-03-31 1995-04-25 Vlsi Technology, Inc. Angled lateral pocket implants on p-type semiconductor devices
US5413945A (en) * 1994-08-12 1995-05-09 United Micro Electronics Corporation Blanket N-LDD implantation for sub-micron MOS device manufacturing
US5478763A (en) * 1995-01-19 1995-12-26 United Microelectronics Corporation High performance field effect transistor and method of manufacture thereof

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