KR960026467A - 반도체 mosfet 제조방법 - Google Patents

반도체 mosfet 제조방법 Download PDF

Info

Publication number
KR960026467A
KR960026467A KR1019940034592A KR19940034592A KR960026467A KR 960026467 A KR960026467 A KR 960026467A KR 1019940034592 A KR1019940034592 A KR 1019940034592A KR 19940034592 A KR19940034592 A KR 19940034592A KR 960026467 A KR960026467 A KR 960026467A
Authority
KR
South Korea
Prior art keywords
gate
forming
insulating film
sidewall
photoresist pattern
Prior art date
Application number
KR1019940034592A
Other languages
English (en)
Other versions
KR0137815B1 (ko
Inventor
강호영
Original Assignee
문정환
Lg 반도체주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, Lg 반도체주식회사 filed Critical 문정환
Priority to KR1019940034592A priority Critical patent/KR0137815B1/ko
Priority to JP07225115A priority patent/JP3098942B2/ja
Priority to US08/573,713 priority patent/US5679592A/en
Publication of KR960026467A publication Critical patent/KR960026467A/ko
Application granted granted Critical
Publication of KR0137815B1 publication Critical patent/KR0137815B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Weting (AREA)

Abstract

본 발명은 반도체 MOS 트랜지스터 제조방법으로서, 가) 반도체 기판에 게이트절연막과 게이트전극을 형성하고, 저농도로 도핑된 불순물영역을 게이트전극 좌우의 기판내에 형성하는 단계, 나) 포토레지스트를 도포한 후, 게이트와 게이트 측면에 사이드월 스페이스 형성부위를 정의하는 포토레지스트패턴을 형성하는 단계, 다) 기판 전면에 절연막을 증착한 후, 이 절연막의 노출된 부위를 일부제거하여 게이트 측면에 사이드월 스페이스를 형성하는 단계와, 라) 상기 포토레지스트패턴을 제거하고, 게이트와 사이드월 측면하부에 고농도로 도핑된 소오스 및 드레인영역을 형성하는 단계를 포함하여 이루어진다.

Description

반도체 MOSFET 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도 및 제3도는 본 발명의 제조공정도이다.

Claims (10)

  1. 반도체 MOS 트랜지스터 제조방법에 있어서, 가) 반도체 기판에 게이트절연막과 게이트전극을 형성하고, 저농도로 도핑된 불순물영역을 게이트전극 좌우의 기판내에 형성하는 단계, 나) 포토레지스트를 도포한 후, 게이트와 게이트 측면에 사이드월 스페이스 형성부위를 정의하는 포토레지스트패턴을 형성하는 단계, 다) 기판 전면에 절연막을 증착한 후, 이 절연막의 노출된 부위를 일부제거하여 게이트 측면에 사이드월스페이스를 형성하는 단계와, 라) 상기 포토레지스트패턴을 제거하고, 게이트와 사이드월 측면하부에 고농도로 도핑된 소오스 및 드레인영역을 형성하는단계를 포함하는 반도체 모스트랜지스트 제조방법.
  2. 제1항에 있어서, 상기 다)단계의 절연막은 저온 화학기상증착방법으로 형성한 산화막을 사용하는 것이 특징인 반도체 모스트랜지스트 제조방법.
  3. 제2항에 있어서, 상기 산화막 증착의 공정온도는 150℃ 이하로 유지하는 것이 특징인 반도체 모스트랜지스트 제조방법.
  4. 제1항에 있어서, 상기 다)단계의 절연막의 제거는 습식식각을 이용하는 것이 특징인 반도체 모스트랜지스트 제조방법.
  5. 제4항에 있어서, 상기 습식식각은 불화물용액을 사용하여 공정을 진행하는 것이 특징인 반도체 모스트랜지스트 제조방법.
  6. 제5항에 있어서, 상기 불화물용액은 완충불산(Buffer HF)을 사용하는 것이 특징인 반도체 모스트랜지스트 제조방법.
  7. 제1항에 있어서, 상기 라)단계의 포토제거는 유기물을 제거할 수 있는 케미컬을 사용하는 것이 특징인 반도체 모스트랜지스트 제조방법.
  8. 제7항에 있어서, 상기 유기물을 제거할 수 있는 케미컬은 H2SO4와 H2O2의 혼합물을 이용하는 것이 특징인 반도체 모스트랜지스트 제조방법.
  9. 제1항에 있어서, 상기 다)단계의 사이드월스페이스는 게이트에 대하여 대칭의 구조를 갖는 것이 특징인 반도체 모스트랜지스트 제조방법.
  10. 제1항에 있어서, 상기 다)단계의 사이드월스페이스는 게이트에 대하여 비대칭 구조를 갖는 것이 특징인 반도체 모스트랜지스트 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940034592A 1994-12-16 1994-12-16 반도체 mosfet 제조방법 KR0137815B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019940034592A KR0137815B1 (ko) 1994-12-16 1994-12-16 반도체 mosfet 제조방법
JP07225115A JP3098942B2 (ja) 1994-12-16 1995-09-01 Ｍｏｓトランジスタの製造方法
US08/573,713 US5679592A (en) 1994-12-16 1995-12-18 Process for formation of LDD MOSFET wing photoresist

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940034592A KR0137815B1 (ko) 1994-12-16 1994-12-16 반도체 mosfet 제조방법

Publications (2)

Publication Number Publication Date
KR960026467A true KR960026467A (ko) 1996-07-22
KR0137815B1 KR0137815B1 (ko) 1998-06-01

Family

ID=19401816

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940034592A KR0137815B1 (ko) 1994-12-16 1994-12-16 반도체 mosfet 제조방법

Country Status (3)

Country Link
US (1) US5679592A (ko)
JP (1) JP3098942B2 (ko)
KR (1) KR0137815B1 (ko)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5909622A (en) * 1996-10-01 1999-06-01 Advanced Micro Devices, Inc. Asymmetrical p-channel transistor formed by nitrided oxide and large tilt angle LDD implant
US5893739A (en) * 1996-10-01 1999-04-13 Advanced Micro Devices, Inc. Asymmetrical P-channel transistor having a boron migration barrier and a selectively formed sidewall spacer
US5985724A (en) * 1996-10-01 1999-11-16 Advanced Micro Devices, Inc. Method for forming asymmetrical p-channel transistor having nitrided oxide patterned to selectively form a sidewall spacer
US5963809A (en) * 1997-06-26 1999-10-05 Advanced Micro Devices, Inc. Asymmetrical MOSFET with gate pattern after source/drain formation
KR100972929B1 (ko) * 2003-04-29 2010-07-28 매그나칩 반도체 유한회사 반도체소자의 제조방법
KR100949665B1 (ko) * 2003-04-29 2010-03-29 매그나칩 반도체 유한회사 반도체소자의 제조방법
US7767508B2 (en) * 2006-10-16 2010-08-03 Advanced Micro Devices, Inc. Method for forming offset spacers for semiconductor device arrangements
US9128218B2 (en) * 2011-12-29 2015-09-08 Visera Technologies Company Limited Microlens structure and fabrication method thereof
US10032906B2 (en) * 2016-04-29 2018-07-24 Samsung Electronics Co., Ltd. Vertical field effect transistor and method of fabricating the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5032530A (en) * 1989-10-27 1991-07-16 Micron Technology, Inc. Split-polysilicon CMOS process incorporating unmasked punchthrough and source/drain implants
JPH05243262A (ja) * 1992-02-28 1993-09-21 Citizen Watch Co Ltd 半導体装置の製造方法
KR960014718B1 (en) * 1993-05-14 1996-10-19 Lg Semicon Co Ltd Method of manufacturing transistor
US5395781A (en) * 1994-02-16 1995-03-07 Micron Technology, Inc. Method of making a semiconductor device using photoresist flow

Also Published As

Publication number Publication date
JPH08186260A (ja) 1996-07-16
US5679592A (en) 1997-10-21
KR0137815B1 (ko) 1998-06-01
JP3098942B2 (ja) 2000-10-16

Similar Documents

Publication Publication Date Title
KR970004078A (ko) 반도체소자 및 그 제조방법
KR960026467A (ko) 반도체 mosfet 제조방법
KR950024341A (ko) 반도체 메모리장치의 제조방법
KR970063780A (ko) 트랜지스터 제조방법
KR960002524A (ko) 3-5족 반도체 구조체 및 그 제조 방법
KR970054431A (ko) 모스 트랜지스터 및 그 제조방법
KR960012576A (ko) 박막 반도체 장치의 제조방법
KR970004079A (ko) 반도체소자 및 그 제조방법
KR970008580A (ko) 반도체 소자의 트랜지스터 제조방법
KR950030397A (ko) 반도체 소자의 캐패시터 형성방법
KR970053015A (ko) 반도체 소자의 트랜지스터 제조방법
KR100236063B1 (ko) 게이트 다결정 실리콘의 식각방법
KR950021269A (ko) 반도체 소자의 소오스/드레인 형성 방법
KR970054257A (ko) 저도핑 드레인 구조의 박막 트랜지스터 및 그 제조 방법
KR920010827A (ko) 반도체 장치의 소자격리 방법
KR950025492A (ko) 폴리실콘 식각시 발생하는 폴리머 제거방법
KR950034622A (ko) 반도체 소자의 트랜지스터 형성방법
KR970077479A (ko) 반도체소자 제조방법
KR950015658A (ko) 반도체소자 제조방법
KR930017207A (ko) Mosfet 제조방법
KR910007104A (ko) 자기정렬콘택(Self-Aligned Contact) 형성방법
KR930015066A (ko) 반도체 장치의 살리사이드 형성방법
KR970077361A (ko) 박막 트랜지스터의 제조방법
KR930015005A (ko) 디램셀의 제조방법
KR940001461A (ko) 박막 트랜지스터의 제조방법

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20050124

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee