KR960016772B1 - 반도체장치로서의 칩주변구조와 그 제조방법 - Google Patents

반도체장치로서의 칩주변구조와 그 제조방법 Download PDF

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Publication number
KR960016772B1
KR960016772B1 KR1019920021590A KR920021590A KR960016772B1 KR 960016772 B1 KR960016772 B1 KR 960016772B1 KR 1019920021590 A KR1019920021590 A KR 1019920021590A KR 920021590 A KR920021590 A KR 920021590A KR 960016772 B1 KR960016772 B1 KR 960016772B1
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KR
South Korea
Prior art keywords
layer
semiconductor device
semiconductor
openings
semiconductor substrate
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Expired - Lifetime
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KR1019920021590A
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English (en)
Korean (ko)
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KR930011167A (ko
Inventor
마사노부 이와사키
가쓰히로 쓰카모도
Original Assignee
미쓰비시덴키 가부시키가이샤
시키모리야
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Publication of KR930011167A publication Critical patent/KR930011167A/ko
Application granted granted Critical
Publication of KR960016772B1 publication Critical patent/KR960016772B1/ko
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H01L2223/5446—Located in scribe lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Dicing (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
KR1019920021590A 1991-11-27 1992-11-17 반도체장치로서의 칩주변구조와 그 제조방법 Expired - Lifetime KR960016772B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP91-312257 1991-11-27
JP3312257A JP2890380B2 (ja) 1991-11-27 1991-11-27 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
KR930011167A KR930011167A (ko) 1993-06-23
KR960016772B1 true KR960016772B1 (ko) 1996-12-20

Family

ID=18027064

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920021590A Expired - Lifetime KR960016772B1 (ko) 1991-11-27 1992-11-17 반도체장치로서의 칩주변구조와 그 제조방법

Country Status (6)

Country Link
US (2) US5945716A (enExample)
JP (1) JP2890380B2 (enExample)
KR (1) KR960016772B1 (enExample)
DE (1) DE4239457C2 (enExample)
IT (1) IT1255960B (enExample)
TW (1) TW222711B (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07176688A (ja) * 1993-12-20 1995-07-14 Mitsubishi Electric Corp 半導体集積回路
US6184118B1 (en) * 1998-03-02 2001-02-06 United Microelectronics Corp. Method for preventing the peeling of the tungsten metal after the metal-etching process
JPH11340167A (ja) 1998-05-22 1999-12-10 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP2000269293A (ja) * 1999-03-18 2000-09-29 Fujitsu Ltd 半導体装置
JP3548061B2 (ja) * 1999-10-13 2004-07-28 三洋電機株式会社 半導体装置の製造方法
US6610592B1 (en) * 2000-04-24 2003-08-26 Taiwan Semiconductor Manufacturing Company Method for integrating low-K materials in semiconductor fabrication
US6630746B1 (en) * 2000-05-09 2003-10-07 Motorola, Inc. Semiconductor device and method of making the same
JP2003197854A (ja) * 2001-12-26 2003-07-11 Nec Electronics Corp 両面接続型半導体装置、多段積層型半導体装置、その製造方法および該半導体装置を搭載した電子部品
JP4434606B2 (ja) 2003-03-27 2010-03-17 株式会社東芝 半導体装置、半導体装置の製造方法
JP2005109145A (ja) 2003-09-30 2005-04-21 Toshiba Corp 半導体装置
FR2893182B1 (fr) * 2005-11-10 2007-12-28 Atmel Grenoble Soc Par Actions Procede de decoupe de puces de circuit-integre sur substrat aminci
ITTO20100332A1 (it) * 2010-04-21 2011-10-22 St Microelectronics Srl Procedimento per la fabbricazione di piastrine semiconduttrici e piastrina semiconduttrice con trincea di protezione
JP2017028056A (ja) * 2015-07-21 2017-02-02 トヨタ自動車株式会社 半導体装置の製造方法
US10109599B2 (en) * 2016-12-21 2018-10-23 Globalfoundries Inc. Integrated circuit structure with continuous metal crack stop
KR102542621B1 (ko) * 2018-08-17 2023-06-15 삼성전자주식회사 반도체 장치
JP7443097B2 (ja) 2020-03-09 2024-03-05 キオクシア株式会社 半導体ウェハおよび半導体チップ
KR20240009279A (ko) * 2022-07-13 2024-01-22 에스케이하이닉스 주식회사 기판 분단을 포함한 반도체 칩 제조 방법

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4392150A (en) * 1980-10-27 1983-07-05 National Semiconductor Corporation MOS Integrated circuit having refractory metal or metal silicide interconnect layer
JPS5776860A (en) * 1980-10-31 1982-05-14 Toshiba Corp Semiconductor device and its manufacture
US5045916A (en) * 1985-01-22 1991-09-03 Fairchild Semiconductor Corporation Extended silicide and external contact technology
US4745081A (en) * 1985-10-31 1988-05-17 International Business Machines Corporation Method of trench filling
JPS63127551A (ja) * 1986-11-17 1988-05-31 Toshiba Corp 半導体装置の製造方法
US4977439A (en) * 1987-04-03 1990-12-11 Esquivel Agerico L Buried multilevel interconnect system
US4879257A (en) * 1987-11-18 1989-11-07 Lsi Logic Corporation Planarization process
JPH01186655A (ja) * 1988-01-14 1989-07-26 Fujitsu Ltd 半導体集積回路
JP2769331B2 (ja) * 1988-09-12 1998-06-25 株式会社日立製作所 半導体集積回路の製造方法
JPH02188942A (ja) * 1989-01-17 1990-07-25 Fujitsu Ltd 多層配線構造を備えた半導体装置の製造方法
JP2737979B2 (ja) * 1989-02-10 1998-04-08 三菱電機株式会社 半導体装置
JPH0750700B2 (ja) * 1989-06-27 1995-05-31 三菱電機株式会社 半導体チップの製造方法
US4987099A (en) * 1989-12-29 1991-01-22 North American Philips Corp. Method for selectively filling contacts or vias or various depths with CVD tungsten

Also Published As

Publication number Publication date
US5945716A (en) 1999-08-31
US6211070B1 (en) 2001-04-03
DE4239457A1 (en) 1993-06-03
ITMI922707A0 (it) 1992-11-26
TW222711B (enExample) 1994-04-21
JP2890380B2 (ja) 1999-05-10
ITMI922707A1 (it) 1994-05-26
KR930011167A (ko) 1993-06-23
JPH05152433A (ja) 1993-06-18
DE4239457C2 (de) 1995-04-06
IT1255960B (it) 1995-11-17

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