KR960012409A - 비지에이(bga) 반도체패키지의 와이어본딩 검사방법 - Google Patents

비지에이(bga) 반도체패키지의 와이어본딩 검사방법 Download PDF

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KR960012409A
KR960012409A KR1019940024280A KR19940024280A KR960012409A KR 960012409 A KR960012409 A KR 960012409A KR 1019940024280 A KR1019940024280 A KR 1019940024280A KR 19940024280 A KR19940024280 A KR 19940024280A KR 960012409 A KR960012409 A KR 960012409A
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wire bonding
bonding inspection
wire
semiconductor package
inspection method
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KR1019940024280A
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KR0131389B1 (ko
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허영욱
염동신
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황인길
아남산업 주식회사
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Priority to KR1019940024280A priority Critical patent/KR0131389B1/ko
Priority to US08/530,558 priority patent/US5712570A/en
Priority to JP7241960A priority patent/JP2703204B2/ja
Publication of KR960012409A publication Critical patent/KR960012409A/ko
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Publication of KR0131389B1 publication Critical patent/KR0131389B1/ko

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Abstract

본 발명은 비지에이(BGA) 반도체패키지의 와이어본딩 검사방법에 관한 것으로서, 비지에이(BGA) 반도체패키지의 PCB에 반도체칩이 안치되는 부위와 콤파운드 수지물의 분리성을 좋게 하기 위한 게이트까지 전도성 금속층을 연결 형성하여 와이어본딩 검사시스템의 탐침과 캐피러리를 게이트와 반도체칩에 각각 접촉시킨 상태에서 반도체칩과 각 리드간에 와이어본딩된 비지에이(BGA) 반도체패키지의 도통을 확인하여 리프트본드(LIFT BOND) 및 미싱와이어(MISSING WIRE)등의 와이어본딩 작업공정상의 불량을 체크하여 양품 및 불량을 검사할 수 있도록 하므로서 와이어본딩작업 및 검수를 원활히 하고 제품의 품질과 신뢰도를 높일 수 있는 것이다.

Description

비지에이 반도체패키지의 와이어본딩 검사방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 비지에이(BGA) 반도체패키지가 PCB로 적용된 리드프레임의 평면도.
제2도는 본 발명의 와이어본딩된 반도체패키지의 검사방법.
제3도는 본 발명에 따른 단층 PCB상태의 반도체패키지 검사방법 구조도.

Claims (8)

  1. 비지에이(BGA) 반도체패키지의 PCB(P)에 반도체칩(C)이 안치되는 부위(L1)와 이곳에서 콤파운드 수지물의 분리성을 좋게 하기 위한 게이트(G)까지의 거리(L2)에 전도성 금속층(L3)을 연결 형성하여 와이어본딩 검사시스템(S)의 탐침(PR)과 캐피러리(CP)를 게이트(G)와 반도체칩(C)에 각각 접촉시킨 상태에서 반도체칩(C)과 각 리드(LD)간에 와이어본딩된 비지에이(BGA) 반도체패키지의 전기적 도통을 확인하여 양품 및 불량을 검사할 수 있도록 한 것을 특징으로 하는 비지에이(BGA) 반도체패키지의 와이어본딩 검사방법.
  2. 제1항에 있어서, 전도성 금속층(L3)을 금(AU)으로 형성한 것을 특징으로 하는 비지에이(BGA) 반도체패키지의 와이어본딩 검사방법.
  3. 제1항에 있어서, 전도성 금속층(L3)을 구리(CU)로 형성한 것을 특징으로 하는 비지에이(BGA) 반도체패키지의 와이어본딩 검사방법.
  4. 제1항에 있어서, 와이어본딩 검사시스템(S)으로 단층PCB(P)에 와이어본딩된 것을 검사할 수 있는 비지에이(BGA) 반도체피키지의 와이어본딩 검사방법.
  5. 제1항에 있어서, 와이어본딩 검사시스템(S)으로 다층PCB(P)에 와이어본딩된 것을 검사할 수 있는 비지에이(BGA) 반도체패키지의 와이어본딩 검사방법.
  6. 제5항에 있어서, 브라인드비어(BL)가 구비된 다층PCB(P)에 와이어본딩된 것을 검사할 수 있는 비지에이(BGA) 반도체패키지의 와이어본딩 검사방법.
  7. 제5항에 있어서, 베리드비어(BU)가 형성된 다층PCB(P)에 와이어본딩된 것을 검사할 수 있는 비지에이(BGA) 반도체패키지의 와이어본딩 검사방법.
  8. 제5항에 있어서, 관통구멍(TH)이 형성된 다층PCB(P)에 와이어본딩된 것을 검사할 수 있는 비지에이(BGA) 반도체패키지의 와이어본딩 검사방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940024280A 1994-09-27 1994-09-27 비지에이 반도체패키지의 와이어본딩 검사방법 KR0131389B1 (ko)

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KR1019940024280A KR0131389B1 (ko) 1994-09-27 1994-09-27 비지에이 반도체패키지의 와이어본딩 검사방법
US08/530,558 US5712570A (en) 1994-09-27 1995-09-19 Method for checking a wire bond of a semiconductor package
JP7241960A JP2703204B2 (ja) 1994-09-27 1995-09-20 ボール・グリッド・アレイ半導体パッケージのワイヤボンディング検査方法

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KR1019940024280A KR0131389B1 (ko) 1994-09-27 1994-09-27 비지에이 반도체패키지의 와이어본딩 검사방법

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KR960012409A true KR960012409A (ko) 1996-04-20
KR0131389B1 KR0131389B1 (ko) 1998-04-14

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KR0131389B1 (ko) 1998-04-14
US5712570A (en) 1998-01-27
JP2703204B2 (ja) 1998-01-26
JPH08115964A (ja) 1996-05-07

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