KR0131389B1 - 비지에이 반도체패키지의 와이어본딩 검사방법 - Google Patents

비지에이 반도체패키지의 와이어본딩 검사방법

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Publication number
KR0131389B1
KR0131389B1 KR1019940024280A KR19940024280A KR0131389B1 KR 0131389 B1 KR0131389 B1 KR 0131389B1 KR 1019940024280 A KR1019940024280 A KR 1019940024280A KR 19940024280 A KR19940024280 A KR 19940024280A KR 0131389 B1 KR0131389 B1 KR 0131389B1
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KR
South Korea
Prior art keywords
wire bonding
wire
semiconductor package
inspection method
bonding inspection
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Application number
KR1019940024280A
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English (en)
Other versions
KR960012409A (ko
Inventor
허영욱
염동신
Original Assignee
황인길
아남산업주식회사
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Application filed by 황인길, 아남산업주식회사 filed Critical 황인길
Priority to KR1019940024280A priority Critical patent/KR0131389B1/ko
Priority to US08/530,558 priority patent/US5712570A/en
Priority to JP7241960A priority patent/JP2703204B2/ja
Publication of KR960012409A publication Critical patent/KR960012409A/ko
Application granted granted Critical
Publication of KR0131389B1 publication Critical patent/KR0131389B1/ko

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  • Engineering & Computer Science (AREA)
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  • Wire Bonding (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

본 발명은 비지에이(BGA) 반도체패키지의 와이어본딩 검사방법에 관한 것으로서, 비지에이(BGA) 반도체패키지의 PCB에 반도체칩이 안치되는 부위와 콤파운드 수지물의 분리성을 좋게 하기 위한 게이트까지 전도성 금속층을 연결 형성하여 와이어본딩 검사시스템의 탐침과 캐피러리를 게이트와 반도체칩에 각각 접촉시킨 상태에서 반도체칩과 각 리드간에 와이어본딩된 비지에이(BGA) 반도체패키지의 도통을 확인하여 리프트본드(LIFT BOND) 및 미싱와이어(MISSING WIRE)등의 와이어본딩 작업공정상의 불량을 체크하여 양품 및 불량을 검사할 수 있도록 하므로서 와이어본딩작업 및 검수를 원활히 하고 제품의 품질과 신뢰도를 높일 수 있는 것이다.

Description

비지에이 반도체패키지의 와이어본딩 검사방법
제1도는 본 발명의 비지에이(BGA) 반도체패키지가 PCB로 적용된 리드프레임의 평면도.
제2도는 본 발명의 와이어본딩된 반도체패키지의 검사방법.
제3도는 본 발명에 따른 단층 PCB상태의 반도체패키지 검사방법 구조도.
제4도는 본 발명에 따른 브라인드 비어가 구비된 PCB상태의 반도체패키지 검사방법 구조도.
제5도는 본 발명에 따른 베리드 비어를 가진 PCB상태의 반도체패키지 검사방법 구조도.
제6도는 본 발명에 따른 관통구멍된 PCB상태의 반도체패키지 검사방법 구조도.
* 도면의 주요부분에 대한 부호의 설명
C : 반도체칩 CP : 캐피러리
G : 게이트 L1 : 반도체칩안치(탑재)부위
L2 : 반도체칩안치부위에서 게이트까지의 거리 L3 : 전도성 금속층
LD : 리드 P:PCB : (리드프레임)
S : 와이어본딩검사 시스템 BL : 브라이언비어
BU : 베리드비어 TH : 관통구멍
본 발명은 비지에이(BGA;BALL GRID ARRAY) 반도체패키지의 와이어본딩 검사방법에 관한 것으로서, 특히 리드프레임이 피씨이비(PCB; PRINTED CIRCUIT BOARD)로 적용되는 비지에이(BGA) 반도체패키지의 제조공정시 와이어본딩(WIRE BONDING)된 반도체패키지의 리프트본드(LIFT BOND; 본딩자국의 부분이 패드나 포스트로부터 전체적으로 일부분이 떨어지거나 들뜬 경우) 및 미싱와이어(MISSING WIRE; 와이어본딩이 되지 않은 상태)를 검사할 수 있도록 한 비지에이(BGA) 반도체패키지의 와이어본딩 검사방법에 관한 것이다.
일반적으로 종래에는 구리합금 리드프레임(COPPER ALLOY LEAD FRAME)의 반도체칩 탑재판이 전기적 접지역활을 함에 따라 반도체칩과 각 리드의 와이어본딩 작업중에 발생하는 리프트본드(LIFT BOND) 또는 미싱와이어(MISSING WIRE)등의 불량이 발생하는 것을 와이어본딩 검사시스템으로 탑재판과 반도체칩을 접촉시켜 전기적 도통을 통해 확인할 수 있도록 하였으나, PCB를 적용시킨 비지에이(BGA) 반도체패키지에 있어서는 반도체칩이 탑재되는 부위가 전기적 도통이 되지않은 격리부분(ISOLATION : 기판부위)으로 되어 있어 전기적 신호에 의해 와이어본딩된 반도체칩과 각 리드사이의 전기적 도통이 되지 않음에 따라 작업자가 시각적으로 와이어본딩된 자재를 검사하므로 인하여 와이어본딩 검사의 정확성을 기여하지 못하였고, 또한 인적, 물적, 시간적손실을 발생시켜 생산성 및 제품의 품질 신뢰도를 약화시키는 문제점이 있었다.
본 발명은 상기와 같은 종래의 문제점을 해결하기 위하여 발명한 것으로서, 비지에이(BGA) 반도체패키지의 PCB에 반도체칩이 안치되는 부위와 콤파운드 수지물의 분리성을 좋게 하기 위한 게이트까지 전도성 금속층을 연결 형성하여 와이어본딩 검사시스템의 탐침과 캐피러리를 게이트와 반도체칩에 각각 접촉시킨 상태에서 반도체칩과 각 리드간에 와이어본딩된 비지에이(BGA) 반도체패키지의 전기적 도통을 실현시켜 리프트본드(LIFT BOND) 및 미싱와이어(MISSING WIRE)등의 와이어본딩 작업공정상의 불량을 체크하여 양품 및 불량을 검사할 수 있는 것을 목적으로 한다.
이하, 첨부된 도면에 의하여 본 발명을 상세하게 설명하면 다음과 같다.
제1도는 본 발명의 비지에이(BGA) 리드프레임 평면도로서 PCB(P)상에 회로가 인쇄된 다수개의 리드(LD) 중앙부에 반도체칩(C)이 탑재되는 부위(L1)를 금(AU) 또는 구리(CU)의 전도성 금속층(L3)을 형성시킨다.
또한 전도성 금속층(L3)은 상기 반도체칩(C)이 탑재되는 부위(L1)에서 콤파운드수지물을 패키지 몰딩 완료후 수지물의 분리성을 좋게 하기 위하여 PCB(P)상의 일측 외부에 형성된 게이트(G)까지의 거리(L2)에 연결 형성시켜 그라운딩(GROUNDING)되도록 한다.
이러한 비지에이(BGA) 반도체패키지의 리드프레임에 반도체칩(C)을 안치시켜 와이어본딩공정에서의 검사를 시행하면 도시된 도면 제2도에서와 같이 와이어본딩 검사시스템(S)의 일측 탐침(PR)을 리드프레임의 PCB(P)상에 구비된 게이트(G)에 접촉시키고, 타측의 패키러리(CP)는 반도체칩(C)상에 접촉시킨다.
이렇게 탐침(PR)과 캐피러리(CP)가 각각 게이트(G)와 반도체칩(C)에 각기 접촉되면, 각 리드(RD)와 반도체칩(C)사이에 와이어본딩된 비지에이(BGA) 반도체패키지는 반도체칩(C)과 접촉된 부위(L1)의 금(AU) 또는 구리(CU)의 전도성 금속체(L3)가 게이트(G)까지의 거리(L2)에 그라운딩됨에 따라 와이어본딩 검사시스템(S)에서 인가되는 전기적 신호가 와이어본딩된 비지에이(BGA) 반도체패키지의 전기도통 및 단락에 따라 와이어본딩 작업중 리프트본드(LIFT BOND) 및 미싱와이어(MISSING WIRE) 불량상태와 양품의 와이어본딩된 리드프레임자재를 검사할 수 있게 한 것이다.
상기한 전도성 금속층(L3)은 전기적 전도성이 좋은 금(AU)이나 구리(CU)로 사용하여 와이어본딩 검사시스템(S)의 체킹성을 좋게 하였고 또한 반도체패키지내의 전기적 회로 특성에 무리가 없도록 하였다.
이와같은 비지에이(BGA) 반도체패키지의 와이어본딩공정을 검사하는 와이어본딩 검사시스템(S)은 도시된 도면 제3도에서와 같이 단층PCB(P)에 와이어본딩된 것을 검사할 수 있도록 반도체칩(C)이 안치되는 PCB(P)에 금 또는 구리로 된 금속층을 구비하여 와이어본딩검사를 할 수 있도록 한다.
이러한 와이어본딩 검사시스템(S)을 이용한 다른 실시예에 있어서는 도시된 도면 제4도에서와 같이 브라인드비어(BLIND VIA;BL)가 구비된 다층PCB(P)에 안치되는 반도체칩(C)과 도통되는 금 또는 구리의 전도성 금속층(L3)을 그라운딩시켜 와이어본딩 검사시스템(S)으로 와이어본딩 검사를 행하도록 하였다.
상기한 와이어본딩 검사시스템(S)을 이용한 또다른 실시예는 도시된 도면 제5도 및 제6도에서와 같이 베리드비어(BURIED VIA;BU)와 관통구멍(THRU HOLE;TH)이 형성된 다층 PCB(P)에 반도체칩(C)이 안치되는 부위에 전도성 금속층(L3)을 그라운딩시켜 와이어본딩 검사시스템(S)의 탐침(PR)과 캐피러리(CP)를 도통될 수 있게 하여 와이어본딩된 비지에이(BGA) 반도패키지를 리프트본드(LIFT BOND) 또는 미싱와이어(MISSING WIRE)등의 불량을 검사할 수 있도록 한 것이다.
이상에서와 같은 본 발명은 비지에이(BGA) 반도체패키지의 PCB에 반도체칩이 안치되는 부위와 이곳에서 콤파운드 수지물의 분리성을 좋게 하기 위한 게이트까지의 거리에 전도성 금속층을 그라운딩시켜 와이어본딩 검사시스템의 탐침과 캐피런리를 게이트와 반도체칩에 각각 접속시킨 상태에서 반도체칩과 각 리드간에 와이어본딩된 비지에이(BGA) 반도체패키지의 전기적 도통으로 리프트본드(LIFT BOND) 및 미싱와이어(MISSING WIRE) 불량과 와이어본딩된 리드프레임 자재의 양품을 검사하므로서, 와이어본딩 공정에서의 와이어본딩 작업 및 검수를 원활히 하여 제품의 생산성을 높이고 제품의 품질과 신로도를 높일 수 있는 효과가 있는 것이다.

Claims (8)

  1. 비지에이(BGA) 반도체패키지의 PCB(P)에 반도체칩(C)이 안치되는 부위(L1)와 이곳에서 콤파운드 수지물의 분리성을 좋게 하기 위한 게이트(G)까지의 거리(L2)에 전도성 금속층(L3)을 연결 형성하여 와이어본딩 검사시스템(S)의 탐침(PR)과 캐피러리(CP)를 게이트(G)와 반도체칩(C)에 각각 접촉시킨 상태에서 반도체칩(C)과 각 리드(LD)간에 와이어본딩된 비지에이(BGA) 반도체패키지의 전기적 도통을 확인하여 양품 및 불량을 검사할 수 있도록 한 것을 특징으로 하는 비지에이(BGA) 반도체패키지의 와이어본딩 검사방법.
  2. 제1항에 있어서, 전도성 금속층(L3)을 금(AU)으로 형성한 것을 특징으로 하는 비지에이(BGA) 반도체패키지의 와이어본딩 검사방법.
  3. 제1항에 있어서, 전도성 금속층(L3)을 구리(CU)로 형성한 것을 특징으로 하는 비지에이(BGA) 반도체패키지의 와이어본딩 검사방법.
  4. 제1항에 있어서, 와이어본딩 검사시스템(S)으로 단층PCB(P)에 와이어본딩된 것을 검사할 수 있는 비지에이(BGA) 반도체피키지의 와이어본딩 검사방법.
  5. 제1항에 있어서, 와이어본딩 검사시스템(S)으로 다층PCB(P)에 와이어본딩된 것을 검사할 수 있는 비지에이(BGA) 반도체패키지의 와이어본딩 검사방법.
  6. 제5항에 있어서, 브라인드비어(BL)가 구비된 다층PCB(P)에 와이어본딩된 것을 검사할 수 있는 비지에이(BGA) 반도체패키지의 와이어본딩 검사방법.
  7. 제5항에 있어서, 베리드비어(BU)가 형성된 다층PCB(P)에 와이어본딩된 것을 검사할 수 있는 비지에이(BGA) 반도체패키지의 와이어본딩 검사방법.
  8. 제5항에 있어서, 관통구멍(TH)이 형성된 다층PCB(P)에 와이어본딩된 것을 검사할 수 있는 비지에이(BGA) 반도체패키지의 와이어본딩 검사방법.
KR1019940024280A 1994-09-27 1994-09-27 비지에이 반도체패키지의 와이어본딩 검사방법 KR0131389B1 (ko)

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KR1019940024280A KR0131389B1 (ko) 1994-09-27 1994-09-27 비지에이 반도체패키지의 와이어본딩 검사방법
US08/530,558 US5712570A (en) 1994-09-27 1995-09-19 Method for checking a wire bond of a semiconductor package
JP7241960A JP2703204B2 (ja) 1994-09-27 1995-09-20 ボール・グリッド・アレイ半導体パッケージのワイヤボンディング検査方法

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