KR950021597A - 반도체 장치의 커패시터 제조방법 - Google Patents

반도체 장치의 커패시터 제조방법 Download PDF

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Publication number
KR950021597A
KR950021597A KR1019930032282A KR930032282A KR950021597A KR 950021597 A KR950021597 A KR 950021597A KR 1019930032282 A KR1019930032282 A KR 1019930032282A KR 930032282 A KR930032282 A KR 930032282A KR 950021597 A KR950021597 A KR 950021597A
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South Korea
Prior art keywords
side wall
conductive
forming
semiconductor device
storage pattern
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KR1019930032282A
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English (en)
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KR0126799B1 (ko
Inventor
노준용
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김광호
삼성전자 주식회사
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019930032282A priority Critical patent/KR0126799B1/ko
Priority to JP6326669A priority patent/JPH07211798A/ja
Priority to US08/365,446 priority patent/US5545582A/en
Publication of KR950021597A publication Critical patent/KR950021597A/ko
Application granted granted Critical
Publication of KR0126799B1 publication Critical patent/KR0126799B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

커패시턴스를 용이하게 증가시킬 수 있는 반도체 장치의 커패시터 제조방법이 개시되어 있다. 반도체기판 상에 제1도전층을 형성하고, 상기 제1도전층 상의 , 커패시터의 스토리지 노드가 형성될 영역을 제외한 영역에 스토리지 패턴을 형성한다. 상기 스토리지 패턴의 측면부에 제1도전성측벽을 형성하고, 상기 스토리지 패턴을 제거한다. 상기 제1도전성측벽의 측면부에 물질측벽을 형성하고, 상기 물질측벽의 측면부에 제2도전성측벽을 형성한 다음, 물질측벽을 제거한다. 공정 단순화를 도모하면서 고집적 메모리셀에서 요구되는 커패시턴스를 확보할 수 있다.

Description

반도체 장치의 커패시터 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도 내지 제6도는 본 발명에 의한 반도체 장치의 커패시터 제조방법을 설명하기 위한 단면도들.

Claims (3)

  1. 반도체 기판상에 제1도전층을 형성하는 단계; 상기 제1도전층 상의, 커패시터의 스토리지 노드가 형성될 영역을 제외한 영역에 스토리지 패턴을 형성하는 단계; 상기 스트리지 패턴의 측면부에 제1도전성측벽을 형성하는 단계; 상기 스토리지 패턴을 제거하는 단계; 상기 제1도전성측벽의 측면부에 물질측벽을 형성하는 단계; 상기 물질측벽의 측면부에 제2도전성측벽을 형성하는 단계; 및 상기 물질측벽을 제거하는 단계를 구비하는 것을 특징으로 하는 반도체 장치의 커패시터 제조방법.
  2. 제1항에 있어서, 상기 물질측벽은 상기 제1도전성측벽들 사이에 매립하도록 형성하는 것을 특징으로 하는 반도체 장치의 커패시터 제조방법.
  3. 제1항에 있어서, 상기 스토리지 패턴 및 물질측벽을 구성하는 물질로, 임의의 이방성식각에 대해 상기 제1도전층과 제1및 제2도전성측벽을 구성하는 물질과는 식각율이 사용하는 것을 특징으로 하는 반도체 장치의 커패시터 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930032282A 1993-12-31 1993-12-31 반도체장치의 커패시터 제조방법 KR0126799B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019930032282A KR0126799B1 (ko) 1993-12-31 1993-12-31 반도체장치의 커패시터 제조방법
JP6326669A JPH07211798A (ja) 1993-12-31 1994-12-28 半導体装置のキャパシター製造方法
US08/365,446 US5545582A (en) 1993-12-31 1994-12-28 Method for manufacturing semiconductor device capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930032282A KR0126799B1 (ko) 1993-12-31 1993-12-31 반도체장치의 커패시터 제조방법

Publications (2)

Publication Number Publication Date
KR950021597A true KR950021597A (ko) 1995-07-26
KR0126799B1 KR0126799B1 (ko) 1997-12-29

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US (1) US5545582A (ko)
JP (1) JPH07211798A (ko)
KR (1) KR0126799B1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980055959A (ko) * 1996-12-28 1998-09-25 김영환 반도체 소자의 캐패시터 제조 방법

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US5665622A (en) * 1995-03-15 1997-09-09 International Business Machines Corporation Folded trench and rie/deposition process for high-value capacitors
US5688713A (en) * 1996-08-26 1997-11-18 Vanguard International Semiconductor Corporation Method of manufacturing a DRAM cell having a double-crown capacitor using polysilicon and nitride spacers
US5677222A (en) * 1996-10-11 1997-10-14 Vanguard International Semiconductor Corporation Method for forming a DRAM capacitor
US5681773A (en) * 1996-10-28 1997-10-28 Vanguard International Semiconductor Corp. Method for forming a DRAM capacitor
US5972769A (en) * 1996-12-20 1999-10-26 Texas Instruments Incoporated Self-aligned multiple crown storage capacitor and method of formation
US5830792A (en) * 1997-05-21 1998-11-03 Vanguard International Semiconductor Corporation Method of making a stack capacitor in a DRAM cell
US5843821A (en) * 1997-06-04 1998-12-01 Vanguard International Semiconductor Corporation Fabrication method for a cylindrical capacitor for a semiconductor device
KR100253086B1 (ko) * 1997-07-25 2000-04-15 윤종용 반도체장치제조를위한세정용조성물및이를이용한반도체장치의제조방법
US5926710A (en) * 1997-10-23 1999-07-20 Vanguard International Semiconductor Corporation Method for making dynamic random access memory cells using a novel stacked capacitor process
US6027981A (en) * 1997-10-27 2000-02-22 Texas Instruments - Acer Incorporated Method for forming a DRAM cell with a fork-shaped capacitor
US5854105A (en) * 1997-11-05 1998-12-29 Vanguard International Semiconductor Corporation Method for making dynamic random access memory cells having double-crown stacked capacitors with center posts
US6518176B2 (en) * 1998-06-05 2003-02-11 Ted Guo Method of selective formation of a barrier layer for a contact level via
US6188100B1 (en) * 1998-08-19 2001-02-13 Micron Technology, Inc. Concentric container fin capacitor
US6174817B1 (en) 1998-08-26 2001-01-16 Texas Instruments Incorporated Two step oxide removal for memory cells
KR100357176B1 (ko) * 1998-12-23 2003-02-19 주식회사 하이닉스반도체 커패시터의구조및제조방법
US6403416B1 (en) 1999-01-07 2002-06-11 Taiwan Semiconductor Manufacturing Company Method for making a double-cylinder-capacitor structure for dynamic random access memory (DRAM)
US6686235B2 (en) * 2001-04-12 2004-02-03 Micron Technology, Inc. Buried digit spacer-separated capacitor array
KR100558005B1 (ko) * 2003-11-17 2006-03-06 삼성전자주식회사 적어도 하나의 스토리지 노드를 갖는 반도체 장치들 및 그제조 방법들
KR100645041B1 (ko) * 2004-07-12 2006-11-10 삼성전자주식회사 엠아이엠 캐패시터를 갖는 반도체 소자 및 그 형성 방법

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980055959A (ko) * 1996-12-28 1998-09-25 김영환 반도체 소자의 캐패시터 제조 방법

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Publication number Publication date
KR0126799B1 (ko) 1997-12-29
US5545582A (en) 1996-08-13
JPH07211798A (ja) 1995-08-11

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