KR950015828A - 이중 주입 후방 확산된 금속산화물 반도체 장치 및 그 형성 방법 - Google Patents

이중 주입 후방 확산된 금속산화물 반도체 장치 및 그 형성 방법 Download PDF

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KR950015828A
KR950015828A KR1019940029237A KR19940029237A KR950015828A KR 950015828 A KR950015828 A KR 950015828A KR 1019940029237 A KR1019940029237 A KR 1019940029237A KR 19940029237 A KR19940029237 A KR 19940029237A KR 950015828 A KR950015828 A KR 950015828A
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semiconductor material
substrate
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injection
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KR1019940029237A
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치앙 마 고든
피러스터파 하산
제이. 애들러 스티븐
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빈센트 비. 인그라시아
모토로라 인코포레이티드
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Publication of KR950015828A publication Critical patent/KR950015828A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

NM0S트랜지스터는 n+ 유형의 반도체 물질로 형성된 드레인과 소스를 갖는다. p형 반도체 물질로 이루어진 기판영역은 소스와 드레인 사이에 위치한다. 게이트 영역은 기판영역 위에 또한 소스 영역과 드레인 영역 사이에 배치된다. 제1 주입 영역은 소스영역과 게이트 영역에 인접하여 배치된다. 제1 주입 영역은 제1 도핑 농도를 갖는 P 형의 반도체 물질로 이루어진다. 제2 주입 영역은 제1 주입 영역과 기판사이에 배치된다. 제2 주입 영역은 제2 도핑 농도를 갖는 P 형의 반도체 물질로 이루어진다. 채널 도핑 모양의 제1 및 제2 주입 영역은 장치 트랜스콘덕턴스를 최대화하기 위해 적절한 내부 전계를 얻도록 고쳐만들어지는 반면에, 동시에 장치 임계 전압과 펀치 쓰루 특성을 제어한다.

Description

이중 주입 후방 확산된 금속산화물 반도체 장치 및 그 형성 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명을 설명하는데 유용한 그래프.

Claims (6)

  1. 제1 유형의 반도체 물질을 갖는 소스 영역 (14)과; 제2 유형의 반도체 물질을 갖는 기판 영역 (16)과; 상기 소스 영역에 인접하여 위치하고, 제1 도핑 농도를 갖는 상기 제2 유형의 반도체 물질을 구비한 제1 주입영역(32) 및 상기 제1주입 영역과 상기 기판사이에 위치하고, 제2 도핑농도를 갖는 제2 유형의 반도체 물질을 구비한 제2 주입 영역을 포함하는 M0S 트랜지스터.
  2. 제1항에 있어서, 상기 기판 영역에 위치한 상기 제1 유형의 반도체 물질을 구비한 드레인영역 (20)을 더 포함하는 MOS 트랜지스터.
  3. 제2항에 있어서, 상기 기판 영역 (16)위에 위치하고 상기 소스 영역 (14)과 상기 드레인영역 (20) 사이에 위치한 게이트 영역 (3)을 더 포함하는 MOS 트랜지스터.
  4. 제1 유형의 반도체 물질을 구비한 소소 영역 (14)을 제공하는 단계와, 제2 유형의 반도체 물질을 구비한 기판영역 (16)을 제공하는 단계와, 제1 도핑 농도를 갖는 제2 유형의 반도체 물질을 구비하는 제1 주입 영역으로 상기 소스 영역에 인접한 제1 주입 영역 (32)을 배치하는 단계 및 제2 도핑 농도를 갖는 상기 제2 유형의 반도체 물질을 구비하는 제2주입 영역으로 상기 제1 주입 영역과 상기 기판사이에 제2 주입 영역(34)을 배치하는 단계를 포함하는 MOS 트랜지스터 형성방법.
  5. 제4항에 있어서, 상기 기판 영역상에 상기 제1 유형의 반도체 물질을 구비한 드레인 영역(20)을 배치하는 단계를 더 포함하는 M0S 트랜지스터 형성방법.
  6. 제5항에 있어서, 상기 기판 영역 위에 위치하고 상기 소소 영역과 상기 드레인 영역 사이에 위치하는 단계를 더 포함하는 MOS 트랜지스터 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940029237A 1993-11-15 1994-11-09 이중 주입 후방 확산된 금속산화물 반도체 장치 및 그 형성 방법 KR950015828A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/153,503 US5371394A (en) 1993-11-15 1993-11-15 Double implanted laterally diffused MOS device and method thereof
US153.503 1993-11-15

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US (1) US5371394A (ko)
EP (1) EP0653795B1 (ko)
JP (1) JPH07183501A (ko)
KR (1) KR950015828A (ko)
CN (1) CN1036816C (ko)
DE (1) DE69419871T2 (ko)
SG (1) SG50467A1 (ko)

Families Citing this family (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3221766B2 (ja) * 1993-04-23 2001-10-22 三菱電機株式会社 電界効果トランジスタの製造方法
DE4340592C2 (de) * 1993-11-29 2002-04-18 Gold Star Electronics Verfahren zum Herstellen eines nichtflüchtigen Halbleiterspeichers und einen nach diesem Verfahren hergestellten Halbleiterspeicher
US5372960A (en) * 1994-01-04 1994-12-13 Motorola, Inc. Method of fabricating an insulated gate semiconductor device
US5466616A (en) * 1994-04-06 1995-11-14 United Microelectronics Corp. Method of producing an LDMOS transistor having reduced dimensions, reduced leakage, and a reduced propensity to latch-up
US5650340A (en) * 1994-08-18 1997-07-22 Sun Microsystems, Inc. Method of making asymmetric low power MOS devices
US6031272A (en) 1994-11-16 2000-02-29 Matsushita Electric Industrial Co., Ltd. MOS type semiconductor device having an impurity diffusion layer with a nonuniform impurity concentration profile in a channel region
US5510279A (en) * 1995-01-06 1996-04-23 United Microelectronics Corp. Method of fabricating an asymmetric lightly doped drain transistor device
US5744372A (en) * 1995-04-12 1998-04-28 National Semiconductor Corporation Fabrication of complementary field-effect transistors each having multi-part channel
KR960042942A (ko) * 1995-05-04 1996-12-21 빈센트 비.인그라시아 반도체 디바이스 형성 방법
JPH08330590A (ja) * 1995-06-05 1996-12-13 Motorola Inc 絶縁ゲート電界効果トランジスタ構造およびその製造方法
US5675166A (en) * 1995-07-07 1997-10-07 Motorola, Inc. FET with stable threshold voltage and method of manufacturing the same
US5716866A (en) * 1995-08-30 1998-02-10 Motorola, Inc. Method of forming a semiconductor device
US6127700A (en) * 1995-09-12 2000-10-03 National Semiconductor Corporation Field-effect transistor having local threshold-adjust doping
US5573961A (en) * 1995-11-09 1996-11-12 Taiwan Semiconductor Manufacturing Company Ltd. Method of making a body contact for a MOSFET device fabricated in an SOI layer
US5681761A (en) * 1995-12-28 1997-10-28 Philips Electronics North America Corporation Microwave power SOI-MOSFET with high conductivity metal gate
US6096610A (en) * 1996-03-29 2000-08-01 Intel Corporation Transistor suitable for high voltage circuit
US5748025A (en) * 1996-03-29 1998-05-05 Intel Corporation Method and apparatus for providing high voltage with a low voltage CMOS integrated circuit
JP3356629B2 (ja) * 1996-07-15 2002-12-16 日本電気株式会社 横型ｍｏｓトランジスタの製造方法
US5770880A (en) * 1996-09-03 1998-06-23 Harris Corporation P-collector H.V. PMOS switch VT adjusted source/drain
US5837572A (en) * 1997-01-10 1998-11-17 Advanced Micro Devices, Inc. CMOS integrated circuit formed by using removable spacers to produce asymmetrical NMOS junctions before asymmetrical PMOS junctions for optimizing thermal diffusivity of dopants implanted therein
US5793089A (en) * 1997-01-10 1998-08-11 Advanced Micro Devices, Inc. Graded MOS transistor junction formed by aligning a sequence of implants to a selectively removable polysilicon sidewall space and oxide thermally grown thereon
US5895955A (en) * 1997-01-10 1999-04-20 Advanced Micro Devices, Inc. MOS transistor employing a removable, dual layer etch stop to protect implant regions from sidewall spacer overetch
US6080614A (en) * 1997-06-30 2000-06-27 Intersil Corp Method of making a MOS-gated semiconductor device with a single diffusion
US6127233A (en) * 1997-12-05 2000-10-03 Texas Instruments Incorporated Lateral MOSFET having a barrier between the source/drain regions and the channel region
US6153487A (en) * 1998-03-17 2000-11-28 Advanced Micro Devices, Inc. Approach for the formation of semiconductor devices which reduces band-to-band tunneling current and short-channel effects
US6048772A (en) * 1998-05-04 2000-04-11 Xemod, Inc. Method for fabricating a lateral RF MOS device with an non-diffusion source-backside connection
US6020611A (en) * 1998-06-10 2000-02-01 Motorola, Inc. Semiconductor component and method of manufacture
US6124610A (en) * 1998-06-26 2000-09-26 Advanced Micro Devices, Inc. Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant
FR2794898B1 (fr) 1999-06-11 2001-09-14 France Telecom Dispositif semi-conducteur a tension de seuil compensee et procede de fabrication
US6509230B1 (en) 1999-06-24 2003-01-21 Lucent Technologies Inc. Non-volatile memory semiconductor device including a graded, grown, high quality oxide layer and associated methods
US6395610B1 (en) 1999-06-24 2002-05-28 Lucent Technologies Inc. Method of making bipolar transistor semiconductor device including graded, grown, high quality oxide layer
US6670242B1 (en) 1999-06-24 2003-12-30 Agere Systems Inc. Method for making an integrated circuit device including a graded, grown, high quality gate oxide layer and a nitride layer
US6551946B1 (en) 1999-06-24 2003-04-22 Agere Systems Inc. Two-step oxidation process for oxidizing a silicon substrate wherein the first step is carried out at a temperature below the viscoelastic temperature of silicon dioxide and the second step is carried out at a temperature above the viscoelastic temperature
US6521496B1 (en) 1999-06-24 2003-02-18 Lucent Technologies Inc. Non-volatile memory semiconductor device including a graded, grown, high quality control gate oxide layer and associated methods
FR2796204B1 (fr) * 1999-07-07 2003-08-08 St Microelectronics Sa Transistor mosfet a canal court
EP1111687B1 (en) * 1999-12-22 2011-06-22 Panasonic Electric Works Co., Ltd. MOS semiconductor device
US20030235957A1 (en) * 2002-06-25 2003-12-25 Samir Chaudhry Method and structure for graded gate oxides on vertical and non-planar surfaces
US6825543B2 (en) * 2000-12-28 2004-11-30 Canon Kabushiki Kaisha Semiconductor device, method for manufacturing the same, and liquid jet apparatus
US6822297B2 (en) * 2001-06-07 2004-11-23 Texas Instruments Incorporated Additional n-type LDD/pocket implant for improving short-channel NMOS ESD robustness
US20030062571A1 (en) * 2001-10-03 2003-04-03 Franca-Neto Luiz M. Low noise microwave transistor based on low carrier velocity dispersion control
US6686627B2 (en) * 2001-12-26 2004-02-03 Sirenza Microdevices, Inc. Multiple conductive plug structure for lateral RF MOS devices
KR100549949B1 (ko) * 2003-12-23 2006-02-07 삼성전자주식회사 리세스 타입 모오스 트랜지스터의 제조방법 및 그의 구조
KR100709069B1 (ko) * 2005-08-19 2007-04-18 전북대학교산학협력단 과잉운반자의 드레인 효율을 높인 이종접합 반도체소자구조 및 이의 제조방법
DE102005060521A1 (de) * 2005-12-09 2007-06-14 Atmel Germany Gmbh DMOS-Transistor mit optimierter Randstruktur
CN101577224B (zh) * 2008-05-05 2011-07-06 中芯国际集成电路制造(北京)有限公司 栅氧化层形成方法
JP5239548B2 (ja) * 2008-06-25 2013-07-17 富士通セミコンダクター株式会社 半導体装置及び半導体装置の製造方法
DE102009006885B4 (de) * 2009-01-30 2011-09-22 Advanced Micro Devices, Inc. Verfahren zum Erzeugen einer abgestuften Wannenimplantation für asymmetrische Transistoren mit kleinen Gateelektrodenabständen und Halbleiterbauelemente
WO2010086153A1 (en) * 2009-01-30 2010-08-05 Advanced Micro Devices, Inc Graded well implantation for asymmetric transistors having reduced gate electrode pitches
US8163619B2 (en) * 2009-03-27 2012-04-24 National Semiconductor Corporation Fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portion along source/drain zone
JP5374553B2 (ja) * 2011-08-01 2013-12-25 ルネサスエレクトロニクス株式会社 半導体装置
US9653459B2 (en) * 2012-07-03 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. MOSFET having source region formed in a double wells region
JP6651957B2 (ja) * 2016-04-06 2020-02-19 株式会社デンソー 半導体装置およびその製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1214615B (it) * 1985-06-19 1990-01-18 Ates Componenti Elettron Transistore mos a canale n con limitazione dell'effetto di perforazione (punch-through) erelativo processo di formazione.
JPS62269362A (ja) * 1986-05-19 1987-11-21 Fujitsu Ltd Ｍｉｓトランジスタおよびその製造方法
JP2698645B2 (ja) * 1988-05-25 1998-01-19 株式会社東芝 Ｍｏｓｆｅｔ
USH986H (en) * 1989-06-09 1991-11-05 International Business Machines Corporation Field effect-transistor with asymmetrical structure
US5536957A (en) * 1990-01-16 1996-07-16 Mitsubishi Denki Kabushiki Kaisha MOS field effect transistor having source/drain regions surrounded by impurity wells
JPH05211328A (ja) * 1992-01-20 1993-08-20 Nec Corp Ｍｏｓトランジスタおよびその製造方法

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EP0653795A3 (en) 1996-01-31
EP0653795A2 (en) 1995-05-17
DE69419871T2 (de) 2000-03-16
CN1106573A (zh) 1995-08-09
DE69419871D1 (de) 1999-09-09
CN1036816C (zh) 1997-12-24
US5371394A (en) 1994-12-06
JPH07183501A (ja) 1995-07-21
SG50467A1 (en) 1998-07-20
EP0653795B1 (en) 1999-08-04

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