KR950012744A - 반도체 집적회로 제조방법 - Google Patents

반도체 집적회로 제조방법 Download PDF

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Publication number
KR950012744A
KR950012744A KR1019940026313A KR19940026313A KR950012744A KR 950012744 A KR950012744 A KR 950012744A KR 1019940026313 A KR1019940026313 A KR 1019940026313A KR 19940026313 A KR19940026313 A KR 19940026313A KR 950012744 A KR950012744 A KR 950012744A
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South Korea
Prior art keywords
layer
forming
opening
material layer
dielectric
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KR1019940026313A
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English (en)
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치티페디 살레쉬
쿠마 난다 아룬
Original Assignee
제이.티.레흐버그
에이티 앤드 티. 코포레이션
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Application filed by 제이.티.레흐버그, 에이티 앤드 티. 코포레이션 filed Critical 제이.티.레흐버그
Publication of KR950012744A publication Critical patent/KR950012744A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02—Pretreatment of the material to be coated
    • C23C16/0272—Deposition of sub-layers, e.g. to promote the adhesion of the main coating
    • C23C16/0281—Deposition of sub-layers, e.g. to promote the adhesion of the main coating of metallic sub-layers
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04—Coating on selected surface areas, e.g. using masks
    • C23C16/045—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C23C16/08—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal halides
    • C23C16/14—Deposition of only one other metal element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Materials Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

텅스텐 플러그와 층을 성형하는 방법이 개시된다. 얇은 폴리 실리콘이나 비정질 실리콘(15)이 접촉 개구내에 형성된다. 실리콘이 (WF6)에 노출되어 텅스텐 플러그(21)를 형성한다.

Description

반도체 집적회로 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1-6도는 본 발명의 실시예를 이해하는데 유용한 횡단면도.

Claims (9)

  1. 기판(11)상에 유전체(13)를 형성시키는 단계와 상기 유전체내에 상기 기판(11)을 노출시키는 개구를 형성시키는 단계를 포함하는 반도체 집적회로 제조방법에 있어서, 폴리 실리콘과 비정질실리콘으로 구성된 그룹에서 선택된 물질층(15)을 상기 개구내에 형성시켜 상기 기판(11)과 유전체(13)을 덮는 단계와 상기 물질층(13)을 WH,에 노출시킴으로써 상기 개구내에 텅스텐 플러그(21)를 형성시키는 단계를 더 포함하는 것을 특징으로 하는 반도체 집적회로 제조방법.
  2. 제1항에 있어서, 상기 기판(11)이 결정 실리콘, 도핑된 실리콘, 에피택셜 실리콘, 폴리 실리콘, 비정질 실리콘, 실리사이드, 알루미늄, 구리와 텅스텐으로 구성된 그룹에서 선택된 물질인 것을 특징으로 하는 반도체 집적회로 제조방법.
  3. 제1항에 있어서, 최소한 하나의 부가적 물질층(25,27)이 상기 기판(11)과 물질층(30) 사이에 형성되는 것을 특징으로 하는 반도체 집적회로 제조방법.
  4. 제1항에 있어서, 상기 물질층(30)의 형성에 앞서 상기 개구내에 티타늄층(25)이 침착되는 것을 특징으로 하는 반도체 집적회로 제조방법.
  5. 제1항에 있어서, 상기 물질층의 형성에 앞서 상기 개구내에 내화 금속층(37)이 형성되는 것을 특징으로 하는 반도체 집적회로 제조방법.
  6. 제5항에 있어서, 상기 물질층의 형성에 앞서 질화 티타늄, 티타늄 텅스텐과 질화 지르코늄으로 구성된 그룹에서 선택된 물질층이 상기 내화 금속층위에 형성되는 것을 특징으로 하는 반도체 집적된로 제조방법.
    법.
  7. 제1항에 있어서, 상기 개구(19)가 실리사이드(37)를 노출시키는 것을 특징으로 하는 반도체 집적회로 제조방법.
  8. 제1항에 있어서. 상기 노출 단계가 상기 유전체(13)를 덮는 텅스텐 블랭킷 층(17)을 생성시키고 상기 블랭킷 층이 제거되는 것을 특징으로 하는 반도체 집적회로 제조방법.
  9. 제1항에 있어서, 상기 노출 단계가 상기 유전체(13)를 덮는 텅스텐 블랭킷 층(17)을 생성시키고 상기 블랭킷 층이 패턴화되어 런너를 형성하는 것을 특징으로 하는 반도체 집적회로 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940026313A 1993-10-22 1994-10-14 반도체 집적회로 제조방법 KR950012744A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14178093A 1993-10-22 1993-10-22
US08/141,780 1993-10-22

Publications (1)

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KR950012744A true KR950012744A (ko) 1995-05-16

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ID=22497219

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US (1) US6323126B1 (ko)
EP (1) EP0651436A1 (ko)
JP (2) JPH07176532A (ko)
KR (1) KR950012744A (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100463597B1 (ko) * 1997-09-29 2005-02-28 주식회사 하이닉스반도체 반도체소자의제조방법

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5963828A (en) * 1996-12-23 1999-10-05 Lsi Logic Corporation Method for tungsten nucleation from WF6 using titanium as a reducing agent
WO2000006795A1 (en) * 1998-07-27 2000-02-10 Applied Materials, Inc. Cvd tungsten deposition on oxide substrates
US6294468B1 (en) * 1999-05-24 2001-09-25 Agere Systems Guardian Corp. Method of chemical vapor depositing tungsten films
CN103378060A (zh) * 2012-04-28 2013-10-30 上海华虹Nec电子有限公司 硅通孔及其填充方法
TWI716511B (zh) * 2015-12-19 2021-01-21 美商應用材料股份有限公司 用於鎢原子層沉積製程作為成核層之正形非晶矽
US10480066B2 (en) 2015-12-19 2019-11-19 Applied Materials, Inc. Metal deposition methods

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0164976B1 (en) * 1984-06-02 1990-10-24 Fujitsu Limited Method of producing a contact for a semiconductor device
JPS62243324A (ja) * 1986-04-15 1987-10-23 Matsushita Electric Ind Co Ltd 半導体集積回路の製造方法
JPS62243325A (ja) * 1986-04-15 1987-10-23 Matsushita Electric Ind Co Ltd 半導体集積回路の製造方法
US5084413A (en) * 1986-04-15 1992-01-28 Matsushita Electric Industrial Co., Ltd. Method for filling contact hole
JPS62243326A (ja) * 1986-04-15 1987-10-23 Matsushita Electric Ind Co Ltd 半導体集積回路の製造方法
JPS6352441A (ja) * 1986-08-22 1988-03-05 Hitachi Ltd 半導体集積回路装置の製造方法
US4960732A (en) * 1987-02-19 1990-10-02 Advanced Micro Devices, Inc. Contact plug and interconnect employing a barrier lining and a backfilled conductor material
JPS63288046A (ja) * 1987-05-20 1988-11-25 Nec Corp 半導体集積回路装置の製造方法
US4994410A (en) * 1988-04-04 1991-02-19 Motorola, Inc. Method for device metallization by forming a contact plug and interconnect using a silicide/nitride process
JPH0290518A (ja) * 1988-09-28 1990-03-30 Hitachi Ltd 半導体装置及びその製造方法
JP2660072B2 (ja) * 1989-11-10 1997-10-08 株式会社東芝 コンタクトの形成方法
US5141897A (en) * 1990-03-23 1992-08-25 At&T Bell Laboratories Method of making integrated circuit interconnection
US5094981A (en) * 1990-04-17 1992-03-10 North American Philips Corporation, Signetics Div. Technique for manufacturing interconnections for a semiconductor device by annealing layers of titanium and a barrier material above 550° C.
JP2751606B2 (ja) * 1990-09-12 1998-05-18 ソニー株式会社 配線の形成方法
JPH04288824A (ja) * 1991-03-18 1992-10-13 Sony Corp ブランケットタングステンによるプラグ形成方法
US5250467A (en) * 1991-03-29 1993-10-05 Applied Materials, Inc. Method for forming low resistance and low defect density tungsten contacts to silicon semiconductor wafer
JPH04307934A (ja) * 1991-04-05 1992-10-30 Sony Corp タングステンプラグの形成方法
JPH04336422A (ja) * 1991-05-13 1992-11-24 Sony Corp 配線形成方法及びその方法に使用するｅｃｒエッチング装置
JPH05144951A (ja) * 1991-09-27 1993-06-11 Sony Corp 配線形成方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100463597B1 (ko) * 1997-09-29 2005-02-28 주식회사 하이닉스반도체 반도체소자의제조방법

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US6323126B1 (en) 2001-11-27
EP0651436A1 (en) 1995-05-03
JPH07176532A (ja) 1995-07-14
JP2008227532A (ja) 2008-09-25

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