KR970077371A - 반도체 집적회로장치와 그 제조방법 - Google Patents
반도체 집적회로장치와 그 제조방법 Download PDFInfo
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- KR970077371A KR970077371A KR1019970020685A KR19970020685A KR970077371A KR 970077371 A KR970077371 A KR 970077371A KR 1019970020685 A KR1019970020685 A KR 1019970020685A KR 19970020685 A KR19970020685 A KR 19970020685A KR 970077371 A KR970077371 A KR 970077371A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 18
- 238000010438 heat treatment Methods 0.000 claims abstract 6
- 239000004020 conductor Substances 0.000 claims 16
- 238000000151 deposition Methods 0.000 claims 6
- 229910052751 metal Inorganic materials 0.000 claims 5
- 239000002184 metal Substances 0.000 claims 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 3
- 238000002844 melting Methods 0.000 claims 3
- 230000008018 melting Effects 0.000 claims 3
- 229910021332 silicide Inorganic materials 0.000 claims 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims 3
- 239000003990 capacitor Substances 0.000 claims 2
- 238000002955 isolation Methods 0.000 claims 2
- 150000002736 metal compounds Chemical class 0.000 claims 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 2
- 229920005591 polysilicon Polymers 0.000 claims 2
- 238000003860 storage Methods 0.000 claims 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 claims 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 1
- 229910052802 copper Inorganic materials 0.000 claims 1
- 239000010949 copper Substances 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- 238000005498 polishing Methods 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 239000010936 titanium Substances 0.000 claims 1
- 229910052719 titanium Inorganic materials 0.000 claims 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims 1
- 229910052721 tungsten Inorganic materials 0.000 claims 1
- 239000010937 tungsten Substances 0.000 claims 1
- 230000008021 deposition Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 abstract 1
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- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H10B12/03—Making the capacitor or connections thereto
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Abstract
MISFET를 갖는 반도체 집적회로장치의 제조기술에 관한 것으로서, MISFET를 갖는 반도체 집적회로장치의 제조공정에 있어서의 열처리공정을 저감할 수 있고, MISFET의 소오스, 드레인과 반도체기판의 얕은 접합을 실현하기 위해, MISFET를 형성한 후의 공정에서 반도체기판상에 퇴적하는 모든 도전막을 500℃이하의 온도에서 퇴적하도록 하고, 또 MISFET를 형성한 후의 공정에서 반도체기판상에 퇴적하는 모든 절연막을 500℃이하의 온도에서 퇴적하도록 하였다.
이렇게 하는 것에 의해, 열처리공정을 저감해서 얕은 접합의 MISFET를 형성할 수 있고, 배선저항을 저감할 수 있으며, MISFET를 갖는 반도체 집적회로 장치의 제조공정을 간략화할 수 있다는 효과가 얻어진다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 실시형태 1인 반도체 집적회로장치의 제조방법을 도시한 반도체기판의 주요부 단면도.
Claims (18)
- MISFET를 갖는 반도체 집적회로장치의 제조방법으로서, MISFET를 형성한 후의 공정에서 반도체기판상에 퇴적하는 모든 도전막을 500℃이하의 온도에서 퇴적하는 것을 특징으로 하는 반도체 집적회로장치의 제조방법.
- 제1항에 있어서, 상기 도전막은 금속 또는 금속화합물로 이루어지는 것을 특징으로 하는 반도체 집적회로장치의 제조방법.
- 제2항에 있어서, 상기 금속은 텅스텐, 알루미늄, 티탄 또는 구리이고, 상기 금속화합물은 티탄 나이트라이드인 것을 특징으로 하는 반도체 집적회로장치의 제조방법.
- MISFET를 갖는 반도체 집적회로장치의 제조방법으로서, MISFET를 형성한 후의 공정에서 반도체기판상에 퇴적하는 모든 절연막을 500℃이하의 온도에서 퇴적하는 것을 특징으로 하는 반도체 집적회로장치의 제조방법.
- 제4항에 있어서, 상기 절연막은 플라즈마 CVD법에 의해 퇴적한 산화실리콘막 또는 플라즈마 CVD법에 의해 퇴적한 질화실리콘막인 것을 특징으로 하는 반도체 집적회로장치의 제조방법.
- 제4항에 있어서, 상기 절연막의 표면을 화학적 기계연마법에 의해 평탄화하는 것을 특징으로 하는 반도체 집적회로장치의 제조방법.
- MISFET를 갖는 반도체 집적회로장치의 제조방법으로서, 반도체기판상에 소자분리영역을 형성한 후 상기 반도체기판상의 활성영역에 MISFET를 형성하는 제1공정 및 상기 MISFET의 상부에 절연막과 도전막을 퇴적해서 배선을 형성하는 제2공정을 갖고, 상기 제2공정에 있어서의 열처리온도의 상한을 상기 제1공정에 있어서의 열처리 온도의 상한보다 낮게 하는 것을 특징으로 하는 반도체 집적회로장치의 제조방법.
- 제7항에 있어서, 상기 제2공정에 있어서의 열처리온도를 공정을 거침에 따라 내리는 것을 특징으로 하는 반도체 집적회로장치의 제조방법.
- 제1항에 있어서, 상기 반도체 집적회로장치는 메모리셀 선택용 MISFET의 상부에 비트선을 배치하고, 상기 비트선의 상부에 정보축적용 용량소자를 배치한 메모리셀을 구비한 DRAM을 갖는 것을 특징으로 하는 반도체 집적회로장치의 제조방법.
- (a) 주면을 갖는 반도체기판, (b) 상기 반도체기판의 주면에 형성된 제1반도체영역, (c) 상기 반도체기판의 주면상에 형성되고 상기 제1반도체영역을 일부 노출하는 제1개구를 갖는 제1절연막, (d) 상기 제1개구내에 형성된 폴리실리콘막으로 이루어지는 제1도체층, (e) 상기 제1절연막상에 위치하고 상기 제1도체층의 일부를 노출하는 제2개구를 갖는 제2절연막 및 (f) 상기 제2개구내에 형성된 제2도체층으로 이루어지고, 상기 제1도체층과 제2도체층의 계면에는 실리사이드층이 형성되어 있는 것을 특징으로 하는 반도체 집적회로장치.
- 제10항에 있어서, 상기 반도체 기판의 주면상에 제3절연막을 거쳐서 형성된 제3도체층 및 상기 반도체기판의 주면에 선택적으로 형성된 제4절연막을 더 갖고, 상기 제1반도체영역은 상기 제4절연막과 상기 제3도체층에 의해 규정된 영역에 형성되어 있는 것을 특징으로 하는 반도체 집적회로장치.
- 제11항에 있어서, 상기 제3도체층의 상부 및 측벽을 둘러싸는 제5절연막을 더 갖고, 상기 제5절연막은 상기 제1절연막에 대해서 에칭선택비가 큰 재질로 이루어지는 것을 특징으로 하는 반도체 집적회로장치.
- 제12항에 있어서, 상기 제1절연막은 산화실리콘막이고, 상기 제5절연막은 질화실리콘막인 것을 특징으로 하는 반도체 집적회로장치.
- 제12항에 있어서, 상기 반도체기판의 주면에 형성된 제2반도체영역 및 상기 제2도체층에 전기적으로 접속된 정보축적용 용량소자를 더 갖고, 상기 제1 및 제2반도체영역 사이에 상기 제3도체층이 위치하는 것을 특징으로 하는 반도체 집적회로장치.
- (a) 반도체기판의 주면에 제1반도체영역을 형성하는 공정, (b) 상기 반도체기판의 주면상에 제1절연막을 퇴적하는 공정, (c) 상기 제1절연막에 상기 제1반도체영역의 일부를 노출하는 제1개구를 형성하는 공정, (d) 상기 제1개구내에 선택적으로 폴리실리콘막으로 이루어지는 제1도체층을 형성하는 공정 (e) 상기 제1도체층 및 제1절연막상에 고융점 금속막을 퇴적하고 열처리를 가하는 것에 의해, 상기 제1도체층상에만 선택적으로 상기 고융점 금속층의 실리사이드막을 형성하는 공정, (f) 상기 고융점 금속층의 실리사이드막을 남기고 상기 제1절연막상의 고융점 금속막을 제거하는 공정, (g) 상기 제1절연막상에 제2절연막을 퇴적하고 상기 고융점 금속층의 실리사이드막의 일부가 노출되는 제2개구를 형성하는 공정 및 (h) 상기 제2개구내에 제2도체층을 형성하는 공정으로 이루어지는 반도체 집적회로장치의 제조방법.
- 제15항에 있어서, 상기 반도체기판의 주면에 제4절연막을 갖는 소자를 분리하여 형성하는 공정, 상기 반도체기판의 주면에 제3절연막을 형성하는 공정 및 상기 제3절연막상에 제3도체층을 형성하는 공정을 더 갖는 것을 특징으로 하는 반도체 집적회로장치의 제조방법.
- 제16항에 있어서, 상기 소자분리는 반도체기판의 주면에 홈을 형성하는 공정 및 상기 홈내에 제4절연막을 선택적으로 매립하는 공정을 갖는 것을 특징으로 하는 반도체 집적회로장치의 제조방법.
- 제16항에 있어서, 상기 제3도체층의 상부 및 측벽에 제5절연막을 형성하는 공정을 더 갖고, 상기 제5절연막은 질화실리콘막이고, 상기 제1절연막은 산화실리콘막인 것을 특징으로 하는 반도체 집적회로장치의 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13795796A JP3563530B2 (ja) | 1996-05-31 | 1996-05-31 | 半導体集積回路装置 |
JP96-137957 | 1996-05-31 |
Publications (2)
Publication Number | Publication Date |
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KR970077371A true KR970077371A (ko) | 1997-12-12 |
KR100483413B1 KR100483413B1 (ko) | 2005-08-17 |
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KR1019970020685A KR100483413B1 (ko) | 1996-05-31 | 1997-05-26 | 반도체집적회로장치와그제조방법 |
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US (1) | US5981369A (ko) |
JP (1) | JP3563530B2 (ko) |
KR (1) | KR100483413B1 (ko) |
TW (1) | TW344098B (ko) |
Families Citing this family (23)
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CN1171304C (zh) | 1995-11-20 | 2004-10-13 | 株式会社日立制作所 | 半导体存储器及其制造方法 |
US6815762B2 (en) * | 1997-05-30 | 2004-11-09 | Hitachi, Ltd. | Semiconductor integrated circuit device and process for manufacturing the same including spacers on bit lines |
JPH1140765A (ja) * | 1997-07-16 | 1999-02-12 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
US6212671B1 (en) * | 1997-10-20 | 2001-04-03 | Mitsubishi Electric System Lsi Design Corporation | Mask pattern data producing apparatus, mask pattern data producing method and semiconductor integrated circuit device |
JP3599548B2 (ja) * | 1997-12-18 | 2004-12-08 | 株式会社日立製作所 | 半導体集積回路装置の製造方法 |
JP3697044B2 (ja) * | 1997-12-19 | 2005-09-21 | 株式会社ルネサステクノロジ | 半導体集積回路装置およびその製造方法 |
JP4931267B2 (ja) * | 1998-01-29 | 2012-05-16 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
KR100268447B1 (ko) * | 1998-08-07 | 2000-10-16 | 윤종용 | 커패시터 및 그의 제조 방법 |
JP2000183313A (ja) * | 1998-12-21 | 2000-06-30 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
US6235593B1 (en) * | 1999-02-18 | 2001-05-22 | Taiwan Semiconductor Manufacturing Company | Self aligned contact using spacers on the ILD layer sidewalls |
US6225203B1 (en) * | 1999-05-03 | 2001-05-01 | Taiwan Semiconductor Manufacturing Company | PE-SiN spacer profile for C2 SAC isolation window |
KR100470165B1 (ko) * | 1999-06-28 | 2005-02-07 | 주식회사 하이닉스반도체 | 반도체소자 제조 방법 |
US6333225B1 (en) * | 1999-08-20 | 2001-12-25 | Micron Technology, Inc. | Integrated circuitry and methods of forming circuitry |
US6291335B1 (en) * | 1999-10-04 | 2001-09-18 | Infineon Technologies Ag | Locally folded split level bitline wiring |
KR100364798B1 (ko) * | 2000-04-03 | 2002-12-16 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 제조 방법 |
KR100331568B1 (ko) * | 2000-05-26 | 2002-04-06 | 윤종용 | 반도체 메모리 소자 및 그 제조방법 |
KR100363091B1 (ko) * | 2000-06-27 | 2002-11-30 | 삼성전자 주식회사 | 자기정합 콘택을 갖는 반도체 메모리소자 및 그 제조방법 |
KR100343653B1 (ko) * | 2000-09-22 | 2002-07-11 | 윤종용 | 금속 실리사이드층을 갖는 반도체 장치 및 그 제조방법 |
KR100363099B1 (ko) * | 2001-01-12 | 2002-12-05 | 삼성전자 주식회사 | 주변회로부의 소오스/드레인 영역에 컨택패드를 갖는반도체 장치의 형성방법 |
US6406968B1 (en) * | 2001-01-23 | 2002-06-18 | United Microelectronics Corp. | Method of forming dynamic random access memory |
KR100388682B1 (ko) * | 2001-03-03 | 2003-06-25 | 삼성전자주식회사 | 반도체 메모리 장치의 스토리지 전극층 및 그 형성방법 |
DE10240423B4 (de) * | 2002-09-02 | 2007-02-22 | Advanced Micro Devices, Inc., Sunnyvale | Halbleiterelement mit einem Feldeffekttransistor und einem passiven Kondensator mit reduziertem Leckstrom und einer verbesserten Kapazität pro Einheitsfläche und Verfahren zu dessen Herstellung |
KR100703984B1 (ko) | 2006-03-22 | 2007-04-09 | 삼성전자주식회사 | 반도체 집적 회로 장치의 제조 방법 및 그 구조 |
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JPS63128750A (ja) * | 1986-11-19 | 1988-06-01 | Toshiba Corp | 半導体装置 |
US4954214A (en) * | 1989-01-05 | 1990-09-04 | Northern Telecom Limited | Method for making interconnect structures for VLSI devices |
US5378652A (en) * | 1989-04-19 | 1995-01-03 | Kabushiki Kaisha Toshiba | Method of making a through hole in multi-layer insulating films |
US6093615A (en) * | 1994-08-15 | 2000-07-25 | Micron Technology, Inc. | Method of fabricating a contact structure having a composite barrier layer between a platinum layer and a polysilicon plug |
US5587338A (en) * | 1995-04-27 | 1996-12-24 | Vanguard International Semiconductor Corporation | Polysilicon contact stud process |
US5854127A (en) * | 1997-03-13 | 1998-12-29 | Micron Technology, Inc. | Method of forming a contact landing pad |
-
1996
- 1996-05-31 JP JP13795796A patent/JP3563530B2/ja not_active Expired - Lifetime
-
1997
- 1997-05-09 TW TW086106203A patent/TW344098B/zh not_active IP Right Cessation
- 1997-05-26 KR KR1019970020685A patent/KR100483413B1/ko not_active IP Right Cessation
- 1997-05-30 US US08/865,864 patent/US5981369A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
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KR100483413B1 (ko) | 2005-08-17 |
TW344098B (en) | 1998-11-01 |
JPH09321247A (ja) | 1997-12-12 |
US5981369A (en) | 1999-11-09 |
JP3563530B2 (ja) | 2004-09-08 |
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