KR940012532A - 반도체 장치 및 제조방법 - Google Patents

반도체 장치 및 제조방법

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Publication number
KR940012532A
KR940012532A KR1019930024105A KR930024105A KR940012532A KR 940012532 A KR940012532 A KR 940012532A KR 1019930024105 A KR1019930024105 A KR 1019930024105A KR 930024105 A KR930024105 A KR 930024105A KR 940012532 A KR940012532 A KR 940012532A
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film
silicon oxide
gas
semiconductor device
silane
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KR1019930024105A
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KR0118105B1 (ko
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가또 다까시
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세끼사와 다까시
후지쓰 가부시끼가이샤
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Publication of KR0118105B1 publication Critical patent/KR0118105B1/ko

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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract

산화막 및/또는 질화막을 가지는 반도체장치 및 그 제조방법이 나타내고 있다. 산화막은 실란계 가스와 물을 주원료가스로 하여 CVD법에 의해 실리콘산화막이 형성된다. 또, 실란계 가스와 물을 주원료가스로 하여 소정플라즈마 에너지로 플라즈마 CVD법에 의해 실란올을 포함하는 막이 형성된다. 그 소정 플라즈마 에너지는 20(W.℃/㎤)이하로 선택된다. 이 실란올을 포함하는 막을 어닐하거나, 산소 또는 암모니아, 플라즈마 처리 함으로써 산화막 또는 질화막이 형성된다.

Description

반도체 장치 및 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제5도는 본 발명의 제1실시예에서 사용되는 배치식 CVD 실리콘 산화막 형성장치의 개략구성을 설명하는 도면.
제7도는 본 발명의 제2실시예에서 사용되는 배치식 CVD 실리콘 산화막 형성장치의 개략구성을 설명하는 도면.

Claims (21)

  1. 적어도 실란계 가스와 물을 원료가스로 하여 CVD법에 의해 산화실리콘을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체장치의 제조방법.
  2. 제1항에 있어서, 상기 원료가스에 유동성 원료를 첨가하는 것을 특징으로 하는 반도체장치의 제조방법.
  3. 제2항에 있어서, 상기 유동성 첨가물은 PH3, B2H6및 AsH3에서 선택된 것을 특징으로 하는 반도체장치의 제조방법.
  4. 제2항에 있어서, 상기 CVD법에 의해 산화실리콘을 형성하는 공정은 상기 실란계 가스에 물, 또는 상기 유동성 첨가물을 간헐적으로 도입하여 행해지는 것을 특징으로 하는 반도체장치의 제조방법.
  5. 제1항에 있어서, 상기 원료가스에 유기실란을 혼합하는 것을 특징으로 하는 반도체장치의 제조방법.
  6. 제1항 내지 제5항에 있어서, 상기 실란계 가스와 물 및 유동성 첨가물, 유기실란의 원료중에서 적어도 1개를 플라즈마 또는 광에 의하여 연속적 또는 펄스적으로 여기하는 것을 특징으로 하는 반도체장치의 제조방법.
  7. 실란계 가스와 물을 원료가스로 하여 CVD법에 의해 실리콘 산화막을 형성하는 제1공정 및, 원료가스에 유기실란을 혼합하고, CVD법에 의해 실리콘산화막을 형성하는 제2공정을 가지고, 복수층의 실리콘산화막을 형성하는 것을 특징으로 하는 반도체장치의 제조방법.
  8. 제7항에 있어서, 상기 제1공정 및 제2공정을 적어도 2회 이상 반복하여 행하는 복수층의 실리콘산화막을 형성하는 것을 특징으로 하는 반도체장치의 제조방법.
  9. 반도체기판상에 모노실란(SiH4)과 수증기(H2O)를 공급하여 CVD법에 의해 형성된 제1의 실리콘산화막, 제1의 실리콘산화막 위에 모노실란(SiH4)과 수증기(H2O)와 산소(O2) 및 TEOS의 혼합가스를 도입하여 CVD법에 의해 형성된 제2의 실리콘산화막, 제2의 실리콘산화막 위에 그 TEOS의 공급을 정지하여, 모노실란(SiH4)과 물의 혼합가스를 공급하여 CVD법에 의해 형성된 제3의 실리콘산화막, 제3의 실리콘산화막 위에 다시 TEOS를 도입하여 제2층과 마찬가지로 형성된 제4의 실리콘산화막 및, 제4의 실리콘산화막에 TEOS의 도입을 정지하고, 모노실란(SiH4)과 수증기(H2O)와 산소(O2)의 혼합가스를 공급하여 CVD법에 의해 제5의 실리콘산화막을 가지는 것을 특징으로 하는 반도체장치.
  10. 실리콘기판에 물과 실란계 가스를 원료가스로 하여 CVD법에 의해 PSG층을 형성하는 공정, 형성된 PSG층을 용융하는 공정 및 용융된 PSG층에 실리콘웨이퍼를 접착하는 공정을 가지는 것을 특징으로 하는 반도체장치의 제조방법.
  11. 기판상에 소정의 두께에 폴리실리콘막을 형성하는 제1의 공정 및 폴리실리콘막중 트랜지스터로서 사용하지 않는 부분을 제거하고, 그후 물과 실란계 가스를 공급하여, 실리콘기판을 소정온도로 유지하여 플라즈마 CVD법에 의해 게이트산화막을 형성하는 제2의 공정을 가지는 것을 특징으로 하는 반도체장치.
  12. 실란계 가스와 H2O를 원료가스로 하여 소정의 플라즈마 에너지 값으로 플라즈마 CVD법에 의해 무기실란올을 함유하는 막을 형성하는 제1의 공정과 무기실란올을 함유하는 막을 어닐 또는 산소플라즈마에 쬐임으로써 실리콘산화막으로 하는 제2의 공정을 포함하는 것을 특징으로 하는 반도체장치의 제조방법.
  13. 제12항에 있어서, 상기 소정의 플라즈마 에너지 값이 20(W.℃/㎤)이하로 하는 것을 특징으로 하는 반도체장치의 제조방법.
  14. 제12항에 있어서, 여기전력을 펄스적으로 인가하여 상기 원료가스를 플라즈마화하도록 한 것을 특징으로 하는 반도체장치의 제조방법.
  15. 실란계 가스와 H2O를 원료가스로 하여 소정의 플라즈마 에너지 값으로 플라즈마 CVD법에 의해 무기실란올을 함유하는 막을 형성하는 제1의 공정과 무기실란올을 함유하는 막을 암모니아, 플라즈마 처리함으로써 질화막으로 처리하는 제2의 공정을 포함하는 것을 특징으로 하는 반도체장치의 제조방법.
  16. 제15항에 있어서, 상기 제1의 공정의 소정의 플라즈마 에너지 값이 20(W.℃/㎤)이하로 하는 것을 특징으로 하는 반도체장치의 제조방법.
  17. 제15항에 있어서, 여기전력을 펄스적으로 인가하여 상기 원료가스를 플라즈마화하도록 한 것을 특징으로 하는 반도체장치의 제조방법.
  18. 실란계 가스와 물을 원료가스로 하여 플라즈마 CVD법에 의해 형성되는 실란올을 포함하지 않은 SiO2막을 형성하는 제1의 공정, SiO2막상에 실란계 가스와 H2O를 원료가스로 하여 소정의 플라즈마 에너지 값으로 플라즈마 CVD법에 의해 무기실란올을 함유하는 막을 형성하는 제2의 공정 및 실란계 가스와 H2O의 공급을 멈추어 암모니아, 플라즈마 처리함으로써 무기실란올을 함유하는 막을 질화막으로 하는 제3의 공정을 가지는 것을 특징으로 하는 반도체장치의 제조방법.
  19. SiO2막과, SiO2막 위에 실란과 H2O를 원료가스로 하여 소정의 플라즈마 에너지 값으로 플라즈마 CVD법에의해 무기실란올을 함유하는 막을 형성하고, 이어서 암모니아, 플라즈마 처리에 의해 무기실란올을 함유하는 막이 질화막에 형성된 막으로서 되는 복합 층간절연막을 가지는 것을 특징으로 하는 반도체장치.
  20. 제19항에 있어서, 상기 질화막을 20nm 이하의 두께로 한 것을 특징으로 하는 반도체장치.
  21. 상기 SiO2막과 질화막으로서 되는 복합층간절연막을 다시금 다수층 가지는 것을 특징으로 하는 반도체장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930024105A 1992-11-20 1993-11-13 반도체 장치 및 제조방법 KR0118105B1 (ko)

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JP2000332010A (ja) * 1999-03-17 2000-11-30 Canon Sales Co Inc 層間絶縁膜の形成方法及び半導体装置
JP2001274148A (ja) * 2000-03-24 2001-10-05 Tokyo Electron Ltd プラズマ処理装置及び方法
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