KR940009702B1 - 데이터전송장치 - Google Patents

데이터전송장치 Download PDF

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Publication number
KR940009702B1
KR940009702B1 KR1019910006491A KR910006491A KR940009702B1 KR 940009702 B1 KR940009702 B1 KR 940009702B1 KR 1019910006491 A KR1019910006491 A KR 1019910006491A KR 910006491 A KR910006491 A KR 910006491A KR 940009702 B1 KR940009702 B1 KR 940009702B1
Authority
KR
South Korea
Prior art keywords
data
address
bus
memory
transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019910006491A
Other languages
English (en)
Korean (ko)
Other versions
KR910018919A (ko
Inventor
유끼오 효오가
카쯔유키 카네꼬
Original Assignee
마쯔시다덴기산교 가부시기가이샤
다니이 아끼오
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 마쯔시다덴기산교 가부시기가이샤, 다니이 아끼오 filed Critical 마쯔시다덴기산교 가부시기가이샤
Publication of KR910018919A publication Critical patent/KR910018919A/ko
Application granted granted Critical
Publication of KR940009702B1 publication Critical patent/KR940009702B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Small-Scale Networks (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
  • Detection And Correction Of Errors (AREA)
  • Bus Control (AREA)
KR1019910006491A 1989-11-29 1991-04-23 데이터전송장치 Expired - Fee Related KR940009702B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP1-310061 1989-11-29
JP2-107234 1990-04-23
JP10723490 1990-04-23

Publications (2)

Publication Number Publication Date
KR910018919A KR910018919A (ko) 1991-11-30
KR940009702B1 true KR940009702B1 (ko) 1994-10-17

Family

ID=14453890

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910006491A Expired - Fee Related KR940009702B1 (ko) 1989-11-29 1991-04-23 데이터전송장치

Country Status (4)

Country Link
US (1) US5388229A (cg-RX-API-DMAC7.html)
EP (1) EP0454064B1 (cg-RX-API-DMAC7.html)
KR (1) KR940009702B1 (cg-RX-API-DMAC7.html)
DE (1) DE69131527T2 (cg-RX-API-DMAC7.html)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3387538B2 (ja) * 1992-02-03 2003-03-17 松下電器産業株式会社 データ転送装置，プロセサエレメント及びデータ転送方法
FI94816C (fi) * 1994-01-17 1995-10-25 Nokia Telecommunications Oy Menetelmä ja järjestelmä statistisesti multipleksoidun ATM-väylän ohjaamiseksi, johon väylään liittyy väyläohjain ja liitäntäyksiköt pakettien eli solujen välittämiseksi väylällä
US5657479A (en) * 1995-12-04 1997-08-12 Silicon Graphics, Inc. Hierarchical display list processing in graphics data retrieval system
US5845145A (en) * 1995-12-21 1998-12-01 Apple Computer, Inc. System for generating and sending a critical-world-first data response packet by creating response packet having data ordered in the order best matching the desired order
US7467193B2 (en) * 2000-08-01 2008-12-16 Qwest Communications International Inc Management of virtual and physical network inventories
WO2004107706A1 (en) * 2003-05-30 2004-12-09 International Business Machines Corporation Detecting network attacks
US20090129869A1 (en) * 2006-04-20 2009-05-21 Freyssinet Method and machine for reinforcing an embedded cylindrical pipe

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5530727A (en) * 1978-08-22 1980-03-04 Nec Corp Information processor
US4258418A (en) * 1978-12-28 1981-03-24 International Business Machines Corporation Variable capacity data buffer system
JPS55119720A (en) * 1979-03-09 1980-09-13 Tokyo Electric Power Co Inc:The Operation processing unit
US4819154A (en) * 1982-12-09 1989-04-04 Sequoia Systems, Inc. Memory back up system with one cache memory and two physically separated main memories
US4833605A (en) * 1984-08-16 1989-05-23 Mitsubishi Denki Kabushiki Kaisha Cascaded information processing module having operation unit, parallel port, and serial port for concurrent data transfer and data processing
US4870704A (en) * 1984-10-31 1989-09-26 Flexible Computer Corporation Multicomputer digital processing system
JPS6275860A (ja) * 1985-09-30 1987-04-07 Toshiba Corp デ−タ転送制御装置
US4847750A (en) * 1986-02-13 1989-07-11 Intelligent Instrumentation, Inc. Peripheral DMA controller for data acquisition system
US4779190A (en) * 1986-12-03 1988-10-18 Ncr Corporation Communication bus interface
US5142628A (en) * 1986-12-26 1992-08-25 Hitachi, Ltd. Microcomputer system for communication
JPS63197232A (ja) * 1987-02-12 1988-08-16 Toshiba Corp マイクロプロセツサ
JPH0831061B2 (ja) * 1987-07-24 1996-03-27 株式会社日立製作所 バツフア制御方式
JPH077375B2 (ja) * 1988-06-17 1995-01-30 日本電気株式会社 バス制御方式
EP0362425B1 (en) * 1988-10-05 2000-01-12 Advanced Micro Devices, Inc. Input/output controller incorporating address mapped input/output windows and read ahead/write behind capabilities

Also Published As

Publication number Publication date
DE69131527T2 (de) 2000-04-27
KR910018919A (ko) 1991-11-30
US5388229A (en) 1995-02-07
DE69131527D1 (de) 1999-09-23
EP0454064B1 (en) 1999-08-18
EP0454064A2 (en) 1991-10-30
EP0454064A3 (cg-RX-API-DMAC7.html) 1994-02-23

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