KR940008791U - 로우 어드레스 스트로브(/ras) 신호의 클램핑 회로 - Google Patents

로우 어드레스 스트로브(/ras) 신호의 클램핑 회로

Info

Publication number
KR940008791U
KR940008791U KR2019920018223U KR920018223U KR940008791U KR 940008791 U KR940008791 U KR 940008791U KR 2019920018223 U KR2019920018223 U KR 2019920018223U KR 920018223 U KR920018223 U KR 920018223U KR 940008791 U KR940008791 U KR 940008791U
Authority
KR
South Korea
Prior art keywords
ras
signal
address strobe
clamping circuit
low address
Prior art date
Application number
KR2019920018223U
Other languages
English (en)
Other versions
KR950003390Y1 (ko
Inventor
김태훈
Original Assignee
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 금성일렉트론 주식회사 filed Critical 금성일렉트론 주식회사
Priority to KR92018223U priority Critical patent/KR950003390Y1/ko
Priority to US08/125,953 priority patent/US5469387A/en
Priority to DE4332583A priority patent/DE4332583B4/de
Priority to JP23814093A priority patent/JP3504961B2/ja
Publication of KR940008791U publication Critical patent/KR940008791U/ko
Application granted granted Critical
Publication of KR950003390Y1 publication Critical patent/KR950003390Y1/ko

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G11C5/146—Substrate bias generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
KR92018223U 1992-09-24 1992-09-24 로우 어드레스 스트로브(/ras) 신호의 클램핑 회로 KR950003390Y1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR92018223U KR950003390Y1 (ko) 1992-09-24 1992-09-24 로우 어드레스 스트로브(/ras) 신호의 클램핑 회로
US08/125,953 US5469387A (en) 1992-09-24 1993-09-23 Circuit for clamping enable clock in a semiconductor memory device
DE4332583A DE4332583B4 (de) 1992-09-24 1993-09-24 Schaltung zum Klemmen eines Freigabetaktsignales für eine Halbleiterspeichervorrichtung
JP23814093A JP3504961B2 (ja) 1992-09-24 1993-09-24 半導体メモリ素子のエネーブル信号クランプ回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR92018223U KR950003390Y1 (ko) 1992-09-24 1992-09-24 로우 어드레스 스트로브(/ras) 신호의 클램핑 회로

Publications (2)

Publication Number Publication Date
KR940008791U true KR940008791U (ko) 1994-04-21
KR950003390Y1 KR950003390Y1 (ko) 1995-04-27

Family

ID=19340613

Family Applications (1)

Application Number Title Priority Date Filing Date
KR92018223U KR950003390Y1 (ko) 1992-09-24 1992-09-24 로우 어드레스 스트로브(/ras) 신호의 클램핑 회로

Country Status (4)

Country Link
US (1) US5469387A (ko)
JP (1) JP3504961B2 (ko)
KR (1) KR950003390Y1 (ko)
DE (1) DE4332583B4 (ko)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5703827A (en) * 1996-02-29 1997-12-30 Monolithic System Technology, Inc. Method and structure for generating a boosted word line voltage and a back bias voltage for a memory array
JP2002501654A (ja) * 1997-05-30 2002-01-15 ミクロン テクノロジー，インコーポレイテッド ２５６Ｍｅｇダイナミックランダムアクセスメモリ
KR100471182B1 (ko) * 2002-09-03 2005-03-10 삼성전자주식회사 레디/비지 핀을 이용하여 내부 전압 레벨을 알리는 반도체메모리 장치
KR100543929B1 (ko) * 2003-11-10 2006-01-23 주식회사 하이닉스반도체 반도체 메모리 소자의 뱅크 액티브/프리차지 커맨드 디코더
US7948272B2 (en) 2003-11-27 2011-05-24 Samsung Electronics Co., Ltd. Input buffer for detecting an input signal
US7187612B2 (en) * 2005-04-29 2007-03-06 Infineon Technologies Ag Memory having power-up circuit
US7986577B2 (en) * 2007-03-19 2011-07-26 Hynix Semiconductor Inc. Precharge voltage supplying circuit

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6159688A (ja) * 1984-08-31 1986-03-27 Hitachi Ltd 半導体集積回路装置
JPS6427094A (en) * 1987-07-23 1989-01-30 Mitsubishi Electric Corp Mos-type semiconductor memory
JPS6441519A (en) * 1987-08-07 1989-02-13 Mitsubishi Electric Corp Semiconductor integrated circuit
KR0134773B1 (ko) * 1988-07-05 1998-04-20 Hitachi Ltd 반도체 기억장치
US4924442A (en) * 1988-09-30 1990-05-08 Micron Technology, Inc. Pull up circuit for digit lines in a semiconductor memory
JP2772530B2 (ja) * 1988-12-05 1998-07-02 三菱電機株式会社 半導体集積回路装置
KR920004385B1 (ko) * 1989-11-18 1992-06-04 삼성전자 주식회사 파워 전원공급시 체인 프리챠아지 회로
JPH04252489A (ja) * 1991-01-28 1992-09-08 Mitsubishi Electric Corp 半導体記憶装置
KR940004482Y1 (ko) * 1991-10-10 1994-07-04 금성일렉트론 주식회사 셑 플레이트 전압 초기 셑업회로

Also Published As

Publication number Publication date
KR950003390Y1 (ko) 1995-04-27
JP3504961B2 (ja) 2004-03-08
DE4332583A1 (de) 1994-03-31
JPH06215573A (ja) 1994-08-05
US5469387A (en) 1995-11-21
DE4332583B4 (de) 2007-06-21

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