KR940007460B1 - 전계효과트랜지스터, 이를 이용한 반도체기억장치 및 전계효과트랜지스터의 제조방법 - Google Patents

전계효과트랜지스터, 이를 이용한 반도체기억장치 및 전계효과트랜지스터의 제조방법 Download PDF

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Publication number
KR940007460B1
KR940007460B1 KR1019910009967A KR910009967A KR940007460B1 KR 940007460 B1 KR940007460 B1 KR 940007460B1 KR 1019910009967 A KR1019910009967 A KR 1019910009967A KR 910009967 A KR910009967 A KR 910009967A KR 940007460 B1 KR940007460 B1 KR 940007460B1
Authority
KR
South Korea
Prior art keywords
conductive layer
region
insulating film
oxide film
impurity diffusion
Prior art date
Application number
KR1019910009967A
Other languages
English (en)
Korean (ko)
Other versions
KR920005814A (ko
Inventor
가유 기요미스
이규 야마규찌
나쓰오 아지고
Original Assignee
미쓰비시 뎅끼 가부시끼가이샤
시기 모리야
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 미쓰비시 뎅끼 가부시끼가이샤, 시기 모리야 filed Critical 미쓰비시 뎅끼 가부시끼가이샤
Publication of KR920005814A publication Critical patent/KR920005814A/ko
Priority to KR1019940004705A priority Critical patent/KR940007464B1/ko
Application granted granted Critical
Publication of KR940007460B1 publication Critical patent/KR940007460B1/ko

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
KR1019910009967A 1990-06-18 1991-06-17 전계효과트랜지스터, 이를 이용한 반도체기억장치 및 전계효과트랜지스터의 제조방법 KR940007460B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940004705A KR940007464B1 (ko) 1990-06-18 1994-03-10 메모리 셀

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2-160802 1990-06-18
JP2160802A JP2564972B2 (ja) 1990-06-18 1990-06-18 半導体記憶装置およびその製造方法

Publications (2)

Publication Number Publication Date
KR920005814A KR920005814A (ko) 1992-04-03
KR940007460B1 true KR940007460B1 (ko) 1994-08-18

Family

ID=15722759

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910009967A KR940007460B1 (ko) 1990-06-18 1991-06-17 전계효과트랜지스터, 이를 이용한 반도체기억장치 및 전계효과트랜지스터의 제조방법

Country Status (4)

Country Link
JP (1) JP2564972B2 (de)
KR (1) KR940007460B1 (de)
DE (1) DE4119918C2 (de)
IT (1) IT1248495B (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2905642B2 (ja) * 1992-01-18 1999-06-14 三菱電機株式会社 半導体装置およびその製造方法
DE4300357C2 (de) * 1992-01-18 1995-06-01 Mitsubishi Electric Corp Herstellungsverfahren für eine Halbleitereinrichtung
DE19640273C1 (de) * 1996-09-30 1998-03-12 Siemens Ag Verfahren zur Herstellung barrierenfreier Halbleiterspeicheranordnungen
JP3185745B2 (ja) 1998-04-01 2001-07-11 日本電気株式会社 半導体メモリセル

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS602784B2 (ja) * 1982-12-20 1985-01-23 富士通株式会社 半導体記憶装置
FR2577339B1 (fr) * 1985-02-12 1991-05-10 Eurotechnique Sa Memoire dynamique en circuit integre
JPH06105774B2 (ja) * 1987-11-17 1994-12-21 富士通株式会社 半導体記憶装置及びその製造方法
JP2682021B2 (ja) * 1988-06-29 1997-11-26 富士通株式会社 半導体メモリ装置
KR940005729B1 (ko) * 1989-06-13 1994-06-23 삼성전자 주식회사 디램셀의 제조방법 및 구조

Also Published As

Publication number Publication date
JPH0449656A (ja) 1992-02-19
JP2564972B2 (ja) 1996-12-18
ITMI911649A0 (it) 1991-06-17
KR920005814A (ko) 1992-04-03
ITMI911649A1 (it) 1992-12-17
DE4119918C2 (de) 1994-08-11
DE4119918A1 (de) 1991-12-19
IT1248495B (it) 1995-01-19

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