ITMI911649A0 - Dispositivo di memoria a semiconduttore e procedimento per la sua fabbricazione - Google Patents

Dispositivo di memoria a semiconduttore e procedimento per la sua fabbricazione

Info

Publication number
ITMI911649A0
ITMI911649A0 IT91MI1649A ITMI911649A ITMI911649A0 IT MI911649 A0 ITMI911649 A0 IT MI911649A0 IT 91MI1649 A IT91MI1649 A IT 91MI1649A IT MI911649 A ITMI911649 A IT MI911649A IT MI911649 A0 ITMI911649 A0 IT MI911649A0
Authority
IT
Italy
Prior art keywords
procedure
manufacture
memory device
semiconductor memory
semiconductor
Prior art date
Application number
IT91MI1649A
Other languages
English (en)
Inventor
Masahiro Shimizu
Takehisa Yamaguchi
Natsuo Ajika
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of ITMI911649A0 publication Critical patent/ITMI911649A0/it
Publication of ITMI911649A1 publication Critical patent/ITMI911649A1/it
Application granted granted Critical
Publication of IT1248495B publication Critical patent/IT1248495B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
ITMI911649A 1990-06-18 1991-06-17 Dispositivo di memoria a semiconduttore e procedimento per la sua fabbricazione. IT1248495B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2160802A JP2564972B2 (ja) 1990-06-18 1990-06-18 半導体記憶装置およびその製造方法

Publications (3)

Publication Number Publication Date
ITMI911649A0 true ITMI911649A0 (it) 1991-06-17
ITMI911649A1 ITMI911649A1 (it) 1992-12-17
IT1248495B IT1248495B (it) 1995-01-19

Family

ID=15722759

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI911649A IT1248495B (it) 1990-06-18 1991-06-17 Dispositivo di memoria a semiconduttore e procedimento per la sua fabbricazione.

Country Status (4)

Country Link
JP (1) JP2564972B2 (it)
KR (1) KR940007460B1 (it)
DE (1) DE4119918C2 (it)
IT (1) IT1248495B (it)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2905642B2 (ja) * 1992-01-18 1999-06-14 三菱電機株式会社 半導体装置およびその製造方法
DE4300357C2 (de) * 1992-01-18 1995-06-01 Mitsubishi Electric Corp Herstellungsverfahren für eine Halbleitereinrichtung
DE19640273C1 (de) * 1996-09-30 1998-03-12 Siemens Ag Verfahren zur Herstellung barrierenfreier Halbleiterspeicheranordnungen
JP3185745B2 (ja) 1998-04-01 2001-07-11 日本電気株式会社 半導体メモリセル

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS602784B2 (ja) * 1982-12-20 1985-01-23 富士通株式会社 半導体記憶装置
FR2577339B1 (fr) * 1985-02-12 1991-05-10 Eurotechnique Sa Memoire dynamique en circuit integre
JPH06105774B2 (ja) * 1987-11-17 1994-12-21 富士通株式会社 半導体記憶装置及びその製造方法
JP2682021B2 (ja) * 1988-06-29 1997-11-26 富士通株式会社 半導体メモリ装置
KR940005729B1 (ko) * 1989-06-13 1994-06-23 삼성전자 주식회사 디램셀의 제조방법 및 구조

Also Published As

Publication number Publication date
JPH0449656A (ja) 1992-02-19
DE4119918A1 (de) 1991-12-19
KR940007460B1 (ko) 1994-08-18
IT1248495B (it) 1995-01-19
JP2564972B2 (ja) 1996-12-18
DE4119918C2 (de) 1994-08-11
KR920005814A (ko) 1992-04-03
ITMI911649A1 (it) 1992-12-17

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970628