KR940006213A - Pb / Bi를 함유하지 않는 퍼로브스카이트를 버퍼층으로서 사용한 Pb / Bi를 함유하는 고유전율 산화물 구조물 및 그 제조방법 - Google Patents

Pb / Bi를 함유하지 않는 퍼로브스카이트를 버퍼층으로서 사용한 Pb / Bi를 함유하는 고유전율 산화물 구조물 및 그 제조방법 Download PDF

Info

Publication number
KR940006213A
KR940006213A KR1019930007401A KR930007401A KR940006213A KR 940006213 A KR940006213 A KR 940006213A KR 1019930007401 A KR1019930007401 A KR 1019930007401A KR 930007401 A KR930007401 A KR 930007401A KR 940006213 A KR940006213 A KR 940006213A
Authority
KR
South Korea
Prior art keywords
dielectric constant
high dielectric
layer
constant oxide
grown
Prior art date
Application number
KR1019930007401A
Other languages
English (en)
Inventor
알. 섬머펠트 스코트
Original Assignee
일리엄 이.힐러
텍사스 인스트루먼츠 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 일리엄 이.힐러, 텍사스 인스트루먼츠 인코포레이티드 filed Critical 일리엄 이.힐러
Publication of KR940006213A publication Critical patent/KR940006213A/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02192—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02293—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/014—Capacitor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/118—Oxide films
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/967—Semiconductor on specified insulator

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Physical Vapour Deposition (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

본 발명은 반도체 회로에 유용한 구조물을 제조하는 방법에 관한 것으로, Pb/Bi를 함유하지 않는 고유전율 산화물층의 버퍼층을 반도체 기판 상에 직접적으로 또는 간접적으로 성장하는 단계, 및 Pb/Bi를 함유하는 고유전율 산화물을 버퍼층 상에 증착하는 단계를 포함한다. 선택적으로, 본 발명은 반도체 회로에 유용한 구조물에 관한 것으로, 반도체 기판(10)상에 직접적으로 또는 간접적으로 배치된 Pb/Bi를 함유하지 않는 고유전율 산화물층의 버퍼층(26), 및 버퍼층 상의 Pb/Bi를 함유하는 고유전율 산화물(28)을 포함한다. 양호하게, 게르마늄층(12)는 반도체 기판 상에 에피택셜식으로 성장되고, 버퍼층은 게르마늄층 상에 성장된다. 기판이 실리콘인 경우, Pb/Bi를 함유하지 않는 고유전율 산화물층의 두께는 양호하게 약 10nm 미만이다. 제2의 Pb/Bi를 함유하지 않는 고유전율 산화물층(30)은 Pb/Bi를 함유하는 고유전율 산화물의 상부에 성장될 수 있고, 도전층(상부 전극 : 32)는 제2의 Pn/Bi를 함유하지 않는 고유전율 산화물층 상에 성장될 수 있다.

Description

Pb/Bi를 함유하지 않는 퍼로브스카이트를 버퍼층으로서 사용한 Pb/Bi를 함유하는 고유전율 산화물 구조물 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1도는 BST 버퍼층을 사용한 다층 구조의 한 실시예를 도시한 단면도,
제2도는 BaZrO3(BZ) 버퍼층을 사용한 다층 구조의 다른 실시예를 도시한 단면도,
제3도는 제2버퍼층과 상부 전극을 사용한 다층 구조의 실시예를 도시한 단면도.

Claims (23)

  1. 반도체 회로에 유용한 구조물을 제조하는 방법에 있어서, Pb/Bi를 함유하지 않는 고유전율 산화물층의 버퍼층을 반도체 기판상에 직ㆍ간접적으로 성장시키는 단계, 및 Pb/Bi를 함유하는 고유전율 산화물을 상기 버퍼층상에 증착시키는 단계를 포함하는 것을 특징으로 하는 제조 방법.
  2. 제1항에 있어서, 게르마늄층은 상기 반도체 기판상에 직 간접적으로 에피택셜식으로 성장되고, 상기 버퍼층은 상기 게르마늄층 상에 성장되는 것을 특징으로 하는 방법.
  3. 제1항에 있어서, 상기 기판은 실리콘인 것을 특징으로 하는 방법.
  4. 제1항에 있어서, 상기 Pb/Bi를 함유하지 않는 고유전율 산화물층의 두께가 10nm 미만인 것을 특징으로 하는 방법.
  5. 제1항에 있어서, 상기 기판은 갈륨 아세나이드인 것을 특징으로 하는 방법.
  6. 제 1항에 있어서, 제2의 Pb/Bi를 함유하지 않는 고유전율 산화물층은 상기 Pb/Bi를 함유하는 고유전율 산화물의 상부에 성장되는 것을 특징으로 하는 방법.
  7. 제6항에 있어서, 도전층은 상기 제2의 Pb/Bi를 함유하는 고유전율 산화물층 상에 성장되는 것을 특징으로 하는 방법.
  8. 제1항에 있어서, 상기 고유전율 산화물이 티타네이트인 것을 특징으로 하는 방법.
  9. 제8항에 있어서, 상기 Pb/Bi를 함유하지 않는 고유전율 산화물은 바륨 스트론튬 티타네이트인 것을 특징으로 하는 방법.
  10. 제1항에 있어서, 상기 Pb/Bi를 함유하는 고유전율 산화물은 납 지르코네이트 티타네이트인 것을 특징으로 하는 방법.
  11. 제1항에 있어서, 상기 Pb/Bi를 함유하는 고유전율 산화물과 Pb/Bi를 함유하지 않는 고유전율 산화물이 강유전체 산화물인 것을 특징으로 하는 방법.
  12. 제1항에 있이서, 상기 Pb/Bi를 함유하지 않는 고유전율 산화물이 에피택셜식으로 성장되는 것을 특징으로 하는 방법.
  13. 제 12항에 있어서, 상기 Pb/Bi를 함유하는 고유전율 산화물이 에피택셜식으로 성장되는 것을 특징으로 하는 방법.
  14. 제2항에 있어서, 상기 게르마늄층은 비-단결정 이산화 실리콘, 질화 실리콘, 또는 이산화 실리콘/질화실리콘층 상에 성장되고, 상기 비-단결정층은 상기 반도체 기판 상에 직접적으로 또는 간접적으로 배치되는 것을 특징으로 하는 방법.
  15. 제1항에 있어서, 금속층은 상기 반도체 기판 상에 직·간접적으로 증착되고, 상기 버퍼층은 상기 금속층상에 성장되는 것을 특징으로 하는 방법.
  16. 반도체 회로에 유용한 구조물에 있어서, 반도체 기판 상에 직ㆍ간접적으로 배치된 Pb/Bi률 함유하지 않는 고유전율 산화물충의 버퍼층, 및 상기 버퍼층상의 Pb/Bi를 함유하는 고유전율 산화물을 포함하는 것을 특징으로 하는 구조물.
  17. 제16항에 있어서, 상기 기판이 실리콘인 것을 특징으로 하는 구조물.
  18. 제17항에 있어서, 게르마늄층은 두께가 1mm 미만이고 상기 실리콘 상에 배치되는 것을 특징으로 하는 구조.
  19. 제18항에 있어서, 상기 Pb/Bi를 함유하지 않는 고유전율 산화물은 단결정인 것을 특징으로 하는 구조물.
  20. 제17항에 있어서, 상기 Pb/Bi를 함유하는 고유전율 산화물은 단결정인 것을 특징으로 하는 구조물.
  21. 제16항에 있어서, 상기 기판은 갈륨 아세나이드인 것을 특징으로 하는 구조물.
  22. 제16항에 있어서, 제2의 Pb/Bi를 함유하지 않는 고유전율 산화물층은 상기 Pb/Bi를 함유하는 고유전율 산화물의 상부에 배치되는 것을 특징으로 하는 구조물.
  23. 제16항에 있어서, 상기 게르마늄층은 비-단결정 이산화 실리콘, 질화 실리콘, 또는 이산화 실리콘/질화 실리콘층 상에 성장되고, 상기 비-단결정층은 상기 반도체 기판상에 직·간접적으로 배치되는 것을 특징으로 하는 구조물.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930007401A 1992-05-01 1993-04-30 Pb / Bi를 함유하지 않는 퍼로브스카이트를 버퍼층으로서 사용한 Pb / Bi를 함유하는 고유전율 산화물 구조물 및 그 제조방법 KR940006213A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US87693092A 1992-05-01 1992-05-01
US7/876,930 1992-05-01

Publications (1)

Publication Number Publication Date
KR940006213A true KR940006213A (ko) 1994-03-23

Family

ID=25368867

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930007401A KR940006213A (ko) 1992-05-01 1993-04-30 Pb / Bi를 함유하지 않는 퍼로브스카이트를 버퍼층으로서 사용한 Pb / Bi를 함유하는 고유전율 산화물 구조물 및 그 제조방법

Country Status (6)

Country Link
US (3) US5393352A (ko)
EP (1) EP0568064B1 (ko)
JP (1) JP3285408B2 (ko)
KR (1) KR940006213A (ko)
DE (1) DE69325614T2 (ko)
TW (1) TW232748B (ko)

Families Citing this family (83)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0568064B1 (en) * 1992-05-01 1999-07-14 Texas Instruments Incorporated Pb/Bi-containing high-dielectric constant oxides using a non-Pb/Bi-containing perovskite as a buffer layer
US6537830B1 (en) 1992-10-23 2003-03-25 Symetrix Corporation Method of making ferroelectric FET with polycrystalline crystallographically oriented ferroelectric material
DE69404189T2 (de) * 1993-03-31 1998-01-08 Texas Instruments Inc Leicht donatoren-dotierte Elektroden für Materialien mit hoher dielektrischer Konstante
US5504041A (en) * 1994-08-01 1996-04-02 Texas Instruments Incorporated Conductive exotic-nitride barrier layer for high-dielectric-constant materials
US5629229A (en) * 1995-07-12 1997-05-13 Sharp Kabushiki Kaisha Metalorganic chemical vapor deposition of (Ba1-x Srx)RuO3 /(Ba1-x Srx)TIO3 /(Ba1-x Srx)TiO3 /(Ba1- Srx)RuO3 capacitors for high dielectric materials
JP3274326B2 (ja) * 1995-09-08 2002-04-15 株式会社東芝 半導体装置およびその製造方法
US5612560A (en) * 1995-10-31 1997-03-18 Northern Telecom Limited Electrode structure for ferroelectric capacitors for integrated circuits
KR100215861B1 (ko) * 1996-03-13 1999-08-16 구본준 유전체 박막 제조방법 및 이를 이용한 반도체 장치제조방법
US6455916B1 (en) 1996-04-08 2002-09-24 Micron Technology, Inc. Integrated circuit devices containing isolated dielectric material
US6023082A (en) * 1996-08-05 2000-02-08 Lockheed Martin Energy Research Corporation Strain-based control of crystal anisotropy for perovskite oxides on semiconductor-based material
EP0851473A3 (en) * 1996-12-23 1998-07-22 Lucent Technologies Inc. Method of making a layer with high dielectric K, gate and capacitor insulator layer and device
US6548854B1 (en) 1997-12-22 2003-04-15 Agere Systems Inc. Compound, high-K, gate and capacitor insulator layer
US6074885A (en) * 1997-11-25 2000-06-13 Radiant Technologies, Inc Lead titanate isolation layers for use in fabricating PZT-based capacitors and similar structures
US6171898B1 (en) 1997-12-17 2001-01-09 Texas Instruments Incorporated Method of fabricating an oxygen-stable layer/diffusion barrier/poly bottom electrode structure for high-K-DRAMS using a disposable-oxide processing
US6180446B1 (en) 1997-12-17 2001-01-30 Texas Instruments Incorporated Method of fabricating an oxygen-stable layer/diffusion barrier/poly bottom electrode structure for high-K DRAMS using disposable-oxide processing
US6184074B1 (en) 1997-12-17 2001-02-06 Texas Instruments Incorporated Method of fabrication a self-aligned polysilicon/diffusion barrier/oxygen stable sidewall bottom electrode structure for high-K DRAMS
US5998225A (en) * 1997-12-17 1999-12-07 Texas Instruments Incorporated Method of fabricating an oxygen-stable layer/diffusion barrier/poly bottom electrode structure for high-K DRAMs using disposable-oxide processing
EP0926739A1 (en) * 1997-12-24 1999-06-30 Texas Instruments Incorporated A structure of and method for forming a mis field effect transistor
KR100436059B1 (ko) * 1997-12-30 2004-12-17 주식회사 하이닉스반도체 강유전체 캐패시터 형성 방법
KR100275121B1 (ko) 1997-12-30 2001-01-15 김영환 강유전체 캐패시터 제조방법
KR100275726B1 (ko) 1997-12-31 2000-12-15 윤종용 강유전체 메모리 장치 및 그 제조 방법
KR100321714B1 (ko) * 1998-12-30 2002-05-09 박종섭 반도체메모리소자의캐패시터제조방법
US6340827B1 (en) * 1999-01-13 2002-01-22 Agere Systems Guardian Corp. Diffusion barrier for use with high dielectric constant materials and electronic devices incorporating same
US6248459B1 (en) 1999-03-22 2001-06-19 Motorola, Inc. Semiconductor structure having a crystalline alkaline earth metal oxide interface with silicon
US6241821B1 (en) 1999-03-22 2001-06-05 Motorola, Inc. Method for fabricating a semiconductor structure having a crystalline alkaline earth metal oxide interface with silicon
US6270568B1 (en) * 1999-07-15 2001-08-07 Motorola, Inc. Method for fabricating a semiconductor structure with reduced leakage current density
US6215644B1 (en) 1999-09-09 2001-04-10 Jds Uniphase Inc. High frequency tunable capacitors
KR100340951B1 (ko) * 1999-11-18 2002-06-22 윤덕용 초고집적도 디램 커패시터용 스트론튬-납 티탄산 박막의 제조방법
US6496351B2 (en) 1999-12-15 2002-12-17 Jds Uniphase Inc. MEMS device members having portions that contact a substrate and associated methods of operating
US6229684B1 (en) 1999-12-15 2001-05-08 Jds Uniphase Inc. Variable capacitor and associated fabrication method
US6479173B1 (en) 1999-12-17 2002-11-12 Motorola, Inc. Semiconductor structure having a crystalline alkaline earth metal silicon nitride/oxide interface with silicon
US6291319B1 (en) * 1999-12-17 2001-09-18 Motorola, Inc. Method for fabricating a semiconductor structure having a stable crystalline interface with silicon
US6392257B1 (en) * 2000-02-10 2002-05-21 Motorola Inc. Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same
US6693033B2 (en) 2000-02-10 2004-02-17 Motorola, Inc. Method of removing an amorphous oxide from a monocrystalline surface
JP2001313429A (ja) * 2000-04-27 2001-11-09 Tdk Corp 積層薄膜その製造方法および電子デバイス
EP1290733A1 (en) * 2000-05-31 2003-03-12 Motorola, Inc. Semiconductor device and method for manufacturing the same
US6427066B1 (en) 2000-06-30 2002-07-30 Motorola, Inc. Apparatus and method for effecting communications among a plurality of remote stations
US6501973B1 (en) 2000-06-30 2002-12-31 Motorola, Inc. Apparatus and method for measuring selected physical condition of an animate subject
US6477285B1 (en) 2000-06-30 2002-11-05 Motorola, Inc. Integrated circuits with optical signal propagation
US6410941B1 (en) 2000-06-30 2002-06-25 Motorola, Inc. Reconfigurable systems using hybrid integrated circuits with optical ports
US6590236B1 (en) 2000-07-24 2003-07-08 Motorola, Inc. Semiconductor structure for use with high-frequency signals
US6555946B1 (en) 2000-07-24 2003-04-29 Motorola, Inc. Acoustic wave device and process for forming the same
JP2004505444A (ja) * 2000-07-24 2004-02-19 モトローラ・インコーポレイテッド 薄膜金属酸化物構造体およびその製造方法
WO2002009187A2 (en) * 2000-07-24 2002-01-31 Motorola, Inc. Heterojunction tunneling diodes and process for fabricating same
US6224669B1 (en) 2000-09-14 2001-05-01 Motorola, Inc. Method for fabricating a semiconductor structure having a crystalline alkaline earth metal oxide interface with silicon
US6638838B1 (en) 2000-10-02 2003-10-28 Motorola, Inc. Semiconductor structure including a partially annealed layer and method of forming the same
US6583034B2 (en) 2000-11-22 2003-06-24 Motorola, Inc. Semiconductor structure including a compliant substrate having a graded monocrystalline layer and methods for fabricating the structure and semiconductor devices including the structure
US6563118B2 (en) 2000-12-08 2003-05-13 Motorola, Inc. Pyroelectric device on a monocrystalline semiconductor substrate and process for fabricating same
US6559471B2 (en) 2000-12-08 2003-05-06 Motorola, Inc. Quantum well infrared photodetector and method for fabricating same
JP2002208678A (ja) * 2001-01-11 2002-07-26 Fujitsu Ltd 半導体装置及びその製造方法
US20020096683A1 (en) * 2001-01-19 2002-07-25 Motorola, Inc. Structure and method for fabricating GaN devices utilizing the formation of a compliant substrate
US6673646B2 (en) 2001-02-28 2004-01-06 Motorola, Inc. Growth of compound semiconductor structures on patterned oxide films and process for fabricating same
US7046719B2 (en) 2001-03-08 2006-05-16 Motorola, Inc. Soft handoff between cellular systems employing different encoding rates
US6593833B2 (en) 2001-04-04 2003-07-15 Mcnc Tunable microwave components utilizing ferroelectric and ferromagnetic composite dielectrics and methods for making same
US6709989B2 (en) 2001-06-21 2004-03-23 Motorola, Inc. Method for fabricating a semiconductor structure including a metal oxide interface with silicon
US20030010992A1 (en) * 2001-07-16 2003-01-16 Motorola, Inc. Semiconductor structure and method for implementing cross-point switch functionality
US6531740B2 (en) 2001-07-17 2003-03-11 Motorola, Inc. Integrated impedance matching and stability network
US6646293B2 (en) 2001-07-18 2003-11-11 Motorola, Inc. Structure for fabricating high electron mobility transistors utilizing the formation of complaint substrates
US6693298B2 (en) 2001-07-20 2004-02-17 Motorola, Inc. Structure and method for fabricating epitaxial semiconductor on insulator (SOI) structures and devices utilizing the formation of a compliant substrate for materials used to form same
US6498358B1 (en) 2001-07-20 2002-12-24 Motorola, Inc. Structure and method for fabricating an electro-optic system having an electrochromic diffraction grating
US6472694B1 (en) 2001-07-23 2002-10-29 Motorola, Inc. Microprocessor structure having a compound semiconductor layer
US6855992B2 (en) * 2001-07-24 2005-02-15 Motorola Inc. Structure and method for fabricating configurable transistor devices utilizing the formation of a compliant substrate for materials used to form the same
US6667196B2 (en) 2001-07-25 2003-12-23 Motorola, Inc. Method for real-time monitoring and controlling perovskite oxide film growth and semiconductor structure formed using the method
US6585424B2 (en) 2001-07-25 2003-07-01 Motorola, Inc. Structure and method for fabricating an electro-rheological lens
US6594414B2 (en) 2001-07-25 2003-07-15 Motorola, Inc. Structure and method of fabrication for an optical switch
US6462360B1 (en) 2001-08-06 2002-10-08 Motorola, Inc. Integrated gallium arsenide communications systems
US6589856B2 (en) 2001-08-06 2003-07-08 Motorola, Inc. Method and apparatus for controlling anti-phase domains in semiconductor structures and devices
US6639249B2 (en) 2001-08-06 2003-10-28 Motorola, Inc. Structure and method for fabrication for a solid-state lighting device
US6673667B2 (en) 2001-08-15 2004-01-06 Motorola, Inc. Method for manufacturing a substantially integral monolithic apparatus including a plurality of semiconductor materials
US20030036217A1 (en) * 2001-08-16 2003-02-20 Motorola, Inc. Microcavity semiconductor laser coupled to a waveguide
US20030071327A1 (en) * 2001-10-17 2003-04-17 Motorola, Inc. Method and apparatus utilizing monocrystalline insulator
EP1502285A2 (en) * 2002-05-07 2005-02-02 ASM America, Inc. Silicon-on-insulator structures and methods
US20040012037A1 (en) * 2002-07-18 2004-01-22 Motorola, Inc. Hetero-integration of semiconductor materials on silicon
US20040069991A1 (en) * 2002-10-10 2004-04-15 Motorola, Inc. Perovskite cuprate electronic device structure and process
US20040070312A1 (en) * 2002-10-10 2004-04-15 Motorola, Inc. Integrated circuit and process for fabricating the same
AU2003302958A1 (en) * 2002-12-17 2004-07-09 Eun, Jaehwan Method for preparation of ferroelectric single crystal film structure using deposition method
US7020374B2 (en) * 2003-02-03 2006-03-28 Freescale Semiconductor, Inc. Optical waveguide structure and method for fabricating the same
US6965128B2 (en) * 2003-02-03 2005-11-15 Freescale Semiconductor, Inc. Structure and method for fabricating semiconductor microresonator devices
US20040164315A1 (en) * 2003-02-25 2004-08-26 Motorola, Inc. Structure and device including a tunneling piezoelectric switch and method of forming same
GB0906105D0 (en) 2009-04-08 2009-05-20 Ulive Entpr Ltd Mixed metal oxides
US8592294B2 (en) * 2010-02-22 2013-11-26 Asm International N.V. High temperature atomic layer deposition of dielectric oxides
EP3670708A1 (en) 2018-12-20 2020-06-24 IMEC vzw Perovskite oxides with a-axis orientation
US11903218B2 (en) * 2020-06-26 2024-02-13 Sandisk Technologies Llc Bonded memory devices and methods of making the same

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU610260B2 (en) * 1987-10-16 1991-05-16 Furukawa Electric Co. Ltd., The Oxide superconductor shaped body and method of manufacturing the same
US5179070A (en) * 1988-04-30 1993-01-12 Sumitomo Electric Industries, Ltd. Semiconductor substrate having a superconducting thin film with a buffer layer in between
JPH05503609A (ja) * 1990-02-26 1993-06-10 シンメトリックス・コーポレーション 電子デバイス、それらの製造法および利用法
JPH0488685A (ja) * 1990-07-31 1992-03-23 Matsushita Electric Ind Co Ltd 薄膜基板およびその製造方法
US5173835A (en) * 1991-10-15 1992-12-22 Motorola, Inc. Voltage variable capacitor
EP0540963B1 (de) * 1991-11-04 1995-08-30 Asea Brown Boveri Ag Speiseschaltung für eine Zweirohr-Hydraulik
US5338951A (en) * 1991-11-06 1994-08-16 Ramtron International Corporation Structure of high dielectric constant metal/dielectric/semiconductor capacitor for use as the storage capacitor in memory devices
EP0540993A1 (en) * 1991-11-06 1993-05-12 Ramtron International Corporation Structure and fabrication of high transconductance MOS field effect transistor using a buffer layer/ferroelectric/buffer layer stack as the gate dielectric
EP0568064B1 (en) * 1992-05-01 1999-07-14 Texas Instruments Incorporated Pb/Bi-containing high-dielectric constant oxides using a non-Pb/Bi-containing perovskite as a buffer layer
US5326721A (en) * 1992-05-01 1994-07-05 Texas Instruments Incorporated Method of fabricating high-dielectric constant oxides on semiconductors using a GE buffer layer
US5471364A (en) * 1993-03-31 1995-11-28 Texas Instruments Incorporated Electrode interface for high-dielectric-constant materials

Also Published As

Publication number Publication date
EP0568064A3 (ko) 1994-04-06
EP0568064B1 (en) 1999-07-14
TW232748B (ko) 1994-10-21
JPH06224184A (ja) 1994-08-12
JP3285408B2 (ja) 2002-05-27
US5393352A (en) 1995-02-28
DE69325614D1 (de) 1999-08-19
EP0568064A2 (en) 1993-11-03
DE69325614T2 (de) 2000-01-13
US5912486A (en) 1999-06-15
US5650646A (en) 1997-07-22

Similar Documents

Publication Publication Date Title
KR940006213A (ko) Pb / Bi를 함유하지 않는 퍼로브스카이트를 버퍼층으로서 사용한 Pb / Bi를 함유하는 고유전율 산화물 구조물 및 그 제조방법
KR940006212A (ko) 게르마늄 버퍼층을 사용하는 반도체상의 고 유전율 산화물 및 그 제조방법
US6255122B1 (en) Amorphous dielectric capacitors on silicon
EP0749167B1 (en) Ferroelectric capacitor for semiconductor integrated circuit and method for manufacturing the same
EP1831930B1 (en) Semiconductor device with a superparaelectric gate insulator
KR100481777B1 (ko) 강유전 메모리 전계-효과 트랜지스터 장치 및 이것의 제조방법
US5355277A (en) Thin film capacitor
WO2003010834A3 (en) Microelectronic piezoelectric structure
US6074885A (en) Lead titanate isolation layers for use in fabricating PZT-based capacitors and similar structures
KR100321709B1 (ko) 질화알루미늄막을 접착막으로 이용한 반도체 메모리 소자의 캐패시터 제조 방법
JP3232661B2 (ja) 半導体記憶装置
KR100518395B1 (ko) Vb원소에 의한 산화물/반도체계면의 안정화 방법과 안정화 반도체
KR19990053224A (ko) 반도체 메모리 장치의 캐패시터 및 그 제조방법
JPH05190797A (ja) 半導体記憶装置
KR20000053449A (ko) 반도체 장치 및 집적회로 디바이스
JPH04206870A (ja) 半導体装置
KR100389894B1 (ko) 씨.비.엔을 이용한 금속-강유전체-반도체 트랜지스터
JPH0561783B2 (ko)
JPH06329497A (ja) 結晶性薄膜の成形法
KR950010877B1 (ko) 산화티타늄 유전층 커패시터 형성방법
KR100207517B1 (ko) 에피텍셜 강유전체 메모리 소자 구조
JPH07335770A (ja) 電界効果トランジスタ
KR20020010158A (ko) 강유전성 트랜지스터 및 그 제조 방법

Legal Events

Date Code Title Description
A201 Request for examination
AMND Amendment
E902 Notification of reason for refusal
AMND Amendment
E601 Decision to refuse application
J201 Request for trial against refusal decision
AMND Amendment
E902 Notification of reason for refusal
B701 Decision to grant