KR940005346B1 - 연속하는 판독/기록 신호들간의 타이밍 분리를 보장하는 컴퓨터 시스템 및 방법 - Google Patents

연속하는 판독/기록 신호들간의 타이밍 분리를 보장하는 컴퓨터 시스템 및 방법 Download PDF

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Publication number
KR940005346B1
KR940005346B1 KR1019900018084A KR900018084A KR940005346B1 KR 940005346 B1 KR940005346 B1 KR 940005346B1 KR 1019900018084 A KR1019900018084 A KR 1019900018084A KR 900018084 A KR900018084 A KR 900018084A KR 940005346 B1 KR940005346 B1 KR 940005346B1
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KR
South Korea
Prior art keywords
read
signal
timing
peripheral device
write
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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KR1019900018084A
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English (en)
Korean (ko)
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KR910010302A (ko
Inventor
프란시스 루이스 토마스
패트릭 톰슨 스텝펜
Original Assignee
인터내셔널 비지네스 머신즈 코포레이션
하워드 지. 피거로아
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Publication of KR910010302A publication Critical patent/KR910010302A/ko
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/4226—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
  • Controls And Circuits For Display Device (AREA)
KR1019900018084A 1989-11-13 1990-11-09 연속하는 판독/기록 신호들간의 타이밍 분리를 보장하는 컴퓨터 시스템 및 방법 Expired - Fee Related KR940005346B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US43705989A 1989-11-13 1989-11-13
US437,059 1989-11-13

Publications (2)

Publication Number Publication Date
KR910010302A KR910010302A (ko) 1991-06-29
KR940005346B1 true KR940005346B1 (ko) 1994-06-17

Family

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Application Number Title Priority Date Filing Date
KR1019900018084A Expired - Fee Related KR940005346B1 (ko) 1989-11-13 1990-11-09 연속하는 판독/기록 신호들간의 타이밍 분리를 보장하는 컴퓨터 시스템 및 방법

Country Status (15)

Country Link
US (1) US5388250A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0428293B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPH077377B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
KR (1) KR940005346B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CN (1) CN1020812C (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
AU (1) AU640695B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CA (1) CA2023998A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE69031206T2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
FI (1) FI905611A7 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
MY (1) MY107731A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
NO (1) NO904908L (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
NZ (1) NZ235802A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
PT (1) PT95850A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
SG (1) SG43746A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
TW (1) TW230244B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

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US5553275A (en) * 1993-07-13 1996-09-03 Intel Corporation Method and apparatus for synchronously detecting phase relationships between a high-frequency clock and a low-frequency clock
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US5821784A (en) * 1995-12-29 1998-10-13 Intel Corporation Method and apparatus for generating 2/N mode bus clock signals
US5802132A (en) * 1995-12-29 1998-09-01 Intel Corporation Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme
US5834956A (en) 1995-12-29 1998-11-10 Intel Corporation Core clock correction in a 2/N mode clocking scheme
US5862373A (en) * 1996-09-06 1999-01-19 Intel Corporation Pad cells for a 2/N mode clocking scheme
US5826067A (en) * 1996-09-06 1998-10-20 Intel Corporation Method and apparatus for preventing logic glitches in a 2/n clocking scheme
US5999995A (en) * 1996-12-27 1999-12-07 Oki Data Corporation Systems for adjusting a transfer rate between a host and a peripheral based on a calculation of the processing rate of the host
WO1999019805A1 (en) 1997-10-10 1999-04-22 Rambus Incorporated Method and apparatus for two step memory write operations
US6401167B1 (en) * 1997-10-10 2002-06-04 Rambus Incorporated High performance cost optimized memory
US6055587A (en) * 1998-03-27 2000-04-25 Adaptec, Inc, Integrated circuit SCSI I/O cell having signal assertion edge triggered timed glitch filter that defines a strobe masking period to protect the contents of data latches
US6087867A (en) * 1998-05-29 2000-07-11 Lsi Logic Corporation Transaction control circuit for synchronizing transactions across asynchronous clock domains
EP0978788A1 (en) * 1998-08-04 2000-02-09 Texas Instruments France Improvements in or relating to direct memory access data transfers
EP0978787A1 (en) * 1998-08-04 2000-02-09 Texas Instruments France Improvements in or relating to transferring data between asynchronous device
TR200103388T2 (tr) * 1999-04-01 2002-05-21 Heeling Sports Limited Heeling aleti ve yöntemi.
US6529570B1 (en) * 1999-09-30 2003-03-04 Silicon Graphics, Inc. Data synchronizer for a multiple rate clock source and method thereof
US7096377B2 (en) * 2002-03-27 2006-08-22 Intel Corporation Method and apparatus for setting timing parameters
US20070121398A1 (en) * 2005-11-29 2007-05-31 Bellows Mark D Memory controller capable of handling precharge-to-precharge restrictions
TWI506443B (zh) * 2012-12-27 2015-11-01 Mediatek Inc 處理器與週邊裝置之間的媒介週邊介面及其通信方法
CN109298248B (zh) * 2018-11-12 2020-12-01 中电科仪器仪表有限公司 一种基于fpga的复杂脉冲调制序列测量电路及方法

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Also Published As

Publication number Publication date
SG43746A1 (en) 1997-11-14
DE69031206T2 (de) 1998-02-12
EP0428293B1 (en) 1997-08-06
EP0428293A3 (en) 1992-02-19
MY107731A (en) 1996-05-30
EP0428293A2 (en) 1991-05-22
JPH077377B2 (ja) 1995-01-30
CN1051801A (zh) 1991-05-29
PT95850A (pt) 1992-07-31
NZ235802A (en) 1994-02-25
KR910010302A (ko) 1991-06-29
AU640695B2 (en) 1993-09-02
TW230244B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1994-09-11
AU6464190A (en) 1991-05-16
NO904908L (no) 1991-05-14
FI905611A7 (fi) 1991-05-14
CN1020812C (zh) 1993-05-19
DE69031206D1 (de) 1997-09-11
JPH03160548A (ja) 1991-07-10
NO904908D0 (no) 1990-11-12
FI905611A0 (fi) 1990-11-13
CA2023998A1 (en) 1991-05-14
US5388250A (en) 1995-02-07

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