NO904908L - Datamaskinsystem. - Google Patents
Datamaskinsystem.Info
- Publication number
- NO904908L NO904908L NO90904908A NO904908A NO904908L NO 904908 L NO904908 L NO 904908L NO 90904908 A NO90904908 A NO 90904908A NO 904908 A NO904908 A NO 904908A NO 904908 L NO904908 L NO 904908L
- Authority
- NO
- Norway
- Prior art keywords
- cpu
- external device
- pulse signals
- marker pulse
- read
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/4226—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Information Transfer Systems (AREA)
- Controls And Circuits For Display Device (AREA)
- Communication Control (AREA)
Abstract
Et datamaskinsystem er tllvelebragt som har Innretning (H) mellom en sentralenhet (CPU) (19) og en ytre anordning (15) som sikrer forenllghet eller kompati- bilitet mellom eksisterende programvare for den ytre anordningen (15) og en CPU (19) som har en hvilken som helst hastighet. Innretningen (11) belgeformer lese- eller skrlve-markeringspulsslgnaler l en overferlngs- syklus mellom den ytre anordningen og nevnte CPU (19) for å sikre at tldsstyrlngsparametre l den ytre anordningen (15) Ikke krenkes av hurtige CPU'er. Dersom balgeformingen bevirker en endring l tldsstyrlngen mellom ferste og andre på hverandre felgende lese- eller skrlve-markerlngspulsslgnaler, tllvelebrlnger Innretningen eller grensesnittet (11) et venteslgnal til nevnte CPU l den hensikt & instruere denne til å utvide overferlngssyklusen av det andre markerlngspuls- slgnalet. I den viste utferelsesformen er en anordning (11) Ifelge oppfinnelsen del av et vldeodelsystem som forbinder en mlkroprosessorenhet (MPU) (19) og en video dlgltal-tll-analog omformer (video DAC ) (15). Skriving eller lesing av fargedata til eller fra nevnte video DAC skjer ved hjelp av Innretningen (11) Ifelge oppfinnelsen. Kevnte MPU (IS) gjeres saktere mens den skriver eller leser fargedata kun når det behaves for å hindre krenknlng av tldsstyrlngsparametrene l nevnte video DAC (15). I dette henseende blir sakterevlrkende MPU'er Ikke straffet av oppfinnelsen, ettersom vente- tllstander Innferés l en overferlngssyklus kun når det er nedvendlg for på ny å avstandssette på hverandre felgende lese- eller skrlve-markerlngspulsslgnaler for å hindre krenkr.lngen av tldsstyrlngsparametre.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US43705989A | 1989-11-13 | 1989-11-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
NO904908D0 NO904908D0 (no) | 1990-11-12 |
NO904908L true NO904908L (no) | 1991-05-14 |
Family
ID=23734893
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
NO90904908A NO904908L (no) | 1989-11-13 | 1990-11-12 | Datamaskinsystem. |
Country Status (15)
Country | Link |
---|---|
US (1) | US5388250A (no) |
EP (1) | EP0428293B1 (no) |
JP (1) | JPH077377B2 (no) |
KR (1) | KR940005346B1 (no) |
CN (1) | CN1020812C (no) |
AU (1) | AU640695B2 (no) |
CA (1) | CA2023998A1 (no) |
DE (1) | DE69031206T2 (no) |
FI (1) | FI905611A0 (no) |
MY (1) | MY107731A (no) |
NO (1) | NO904908L (no) |
NZ (1) | NZ235802A (no) |
PT (1) | PT95850A (no) |
SG (1) | SG43746A1 (no) |
TW (1) | TW230244B (no) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5481675A (en) * | 1992-05-12 | 1996-01-02 | International Business Machines Corporation | Asynchronous serial communication system for delaying with software dwell time a receiving computer's acknowledgement in order for the transmitting computer to see the acknowledgement |
KR950008661B1 (ko) * | 1993-05-20 | 1995-08-04 | 현대전자산업주식회사 | 버스 다중화 회로 |
US5537582A (en) * | 1993-05-21 | 1996-07-16 | Draeger; Jeffrey S. | Bus interface circuitry for synchronizing central processors running at multiple clock frequencies to other computer system circuitry |
US5553275A (en) * | 1993-07-13 | 1996-09-03 | Intel Corporation | Method and apparatus for synchronously detecting phase relationships between a high-frequency clock and a low-frequency clock |
JP2551338B2 (ja) * | 1993-07-23 | 1996-11-06 | 日本電気株式会社 | 情報処理装置 |
US5802132A (en) * | 1995-12-29 | 1998-09-01 | Intel Corporation | Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme |
US5834956A (en) | 1995-12-29 | 1998-11-10 | Intel Corporation | Core clock correction in a 2/N mode clocking scheme |
US5821784A (en) * | 1995-12-29 | 1998-10-13 | Intel Corporation | Method and apparatus for generating 2/N mode bus clock signals |
US5862373A (en) * | 1996-09-06 | 1999-01-19 | Intel Corporation | Pad cells for a 2/N mode clocking scheme |
US5826067A (en) * | 1996-09-06 | 1998-10-20 | Intel Corporation | Method and apparatus for preventing logic glitches in a 2/n clocking scheme |
US5999995A (en) * | 1996-12-27 | 1999-12-07 | Oki Data Corporation | Systems for adjusting a transfer rate between a host and a peripheral based on a calculation of the processing rate of the host |
US6401167B1 (en) | 1997-10-10 | 2002-06-04 | Rambus Incorporated | High performance cost optimized memory |
US6343352B1 (en) | 1997-10-10 | 2002-01-29 | Rambus Inc. | Method and apparatus for two step memory write operations |
US6055587A (en) * | 1998-03-27 | 2000-04-25 | Adaptec, Inc, | Integrated circuit SCSI I/O cell having signal assertion edge triggered timed glitch filter that defines a strobe masking period to protect the contents of data latches |
US6087867A (en) * | 1998-05-29 | 2000-07-11 | Lsi Logic Corporation | Transaction control circuit for synchronizing transactions across asynchronous clock domains |
EP0978788A1 (en) * | 1998-08-04 | 2000-02-09 | Texas Instruments France | Improvements in or relating to direct memory access data transfers |
EP0978787A1 (en) * | 1998-08-04 | 2000-02-09 | Texas Instruments France | Improvements in or relating to transferring data between asynchronous device |
WO2000059323A1 (en) * | 1999-04-01 | 2000-10-12 | Heeling Sports Limited | Heeling apparatus and method |
US6529570B1 (en) * | 1999-09-30 | 2003-03-04 | Silicon Graphics, Inc. | Data synchronizer for a multiple rate clock source and method thereof |
US7096377B2 (en) * | 2002-03-27 | 2006-08-22 | Intel Corporation | Method and apparatus for setting timing parameters |
US20070121398A1 (en) * | 2005-11-29 | 2007-05-31 | Bellows Mark D | Memory controller capable of handling precharge-to-precharge restrictions |
TWI506443B (zh) * | 2012-12-27 | 2015-11-01 | Mediatek Inc | 處理器與週邊裝置之間的媒介週邊介面及其通信方法 |
CN109298248B (zh) * | 2018-11-12 | 2020-12-01 | 中电科仪器仪表有限公司 | 一种基于fpga的复杂脉冲调制序列测量电路及方法 |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3587044A (en) * | 1969-07-14 | 1971-06-22 | Ibm | Digital communication system |
US3623017A (en) * | 1969-10-22 | 1971-11-23 | Sperry Rand Corp | Dual clocking arrangement for a digital computer |
US4050096A (en) * | 1974-10-30 | 1977-09-20 | Motorola, Inc. | Pulse expanding system for microprocessor systems with slow memory |
US4050097A (en) * | 1976-09-27 | 1977-09-20 | Honeywell Information Systems, Inc. | Synchronization technique for data transfers over an asynchronous common bus network coupling data processing apparatus |
US4144562A (en) * | 1977-06-23 | 1979-03-13 | Ncr Corporation | System and method for increasing microprocessor output data rate |
US4143418A (en) * | 1977-09-21 | 1979-03-06 | Sperry Rand Corporation | Control device and method for reading a data character from a computer at a fast rate and transmitting the character at a slow rate on a communication line |
US4164787A (en) * | 1977-11-09 | 1979-08-14 | Bell Telephone Laboratories, Incorporated | Multiple microprocessor intercommunication arrangement |
DE2812242A1 (de) * | 1978-03-21 | 1979-10-04 | Bosch Gmbh Robert | Programmierbare ablaufsteuerung |
US4262331A (en) * | 1978-10-30 | 1981-04-14 | Ibm Corporation | Self-adaptive computer load control |
US4539635A (en) * | 1980-02-11 | 1985-09-03 | At&T Bell Laboratories | Pipelined digital processor arranged for conditional operation |
US4494196A (en) * | 1981-05-19 | 1985-01-15 | Wang Laboratories, Inc. | Controller for peripheral data storage units |
US4476527A (en) * | 1981-12-10 | 1984-10-09 | Data General Corporation | Synchronous data bus with automatically variable data rate |
US4517641A (en) * | 1982-04-30 | 1985-05-14 | International Business Machines Corporation | Lookahead I/O device control subsystem |
US4807109A (en) * | 1983-11-25 | 1989-02-21 | Intel Corporation | High speed synchronous/asynchronous local bus and data transfer method |
JPS61255392A (ja) * | 1985-05-09 | 1986-11-13 | 横河電機株式会社 | カラ−画像表示装置 |
FR2586118B1 (fr) * | 1985-08-06 | 1990-01-05 | Bull Sems | Procede d'echange de donnees entre un microprocesseur et une memoire et dispositif permettant la mise en oeuvre du procede |
JPS6243764A (ja) * | 1985-08-21 | 1987-02-25 | Nec Corp | バス・ステ−ト制御回路 |
JP2520872B2 (ja) * | 1985-12-10 | 1996-07-31 | オリンパス光学工業株式会社 | 画像表示装置 |
US4769632A (en) * | 1986-02-10 | 1988-09-06 | Inmos Limited | Color graphics control system |
US4888684A (en) * | 1986-03-28 | 1989-12-19 | Tandem Computers Incorporated | Multiprocessor bus protocol |
JPH0619760B2 (ja) * | 1986-04-23 | 1994-03-16 | 日本電気株式会社 | 情報処理装置 |
JPS6354655A (ja) * | 1986-08-25 | 1988-03-09 | Hitachi Ltd | バスタイミング制御回路 |
AU596459B2 (en) * | 1986-10-17 | 1990-05-03 | Fujitsu Limited | Data transfer system having transfer discrimination circuit |
JPS63155340A (ja) * | 1986-12-19 | 1988-06-28 | Fujitsu Ltd | 記憶装置の読出し方式 |
US4851995A (en) * | 1987-06-19 | 1989-07-25 | International Business Machines Corporation | Programmable variable-cycle clock circuit for skew-tolerant array processor architecture |
US5151986A (en) * | 1987-08-27 | 1992-09-29 | Motorola, Inc. | Microcomputer with on-board chip selects and programmable bus stretching |
US5125084A (en) * | 1988-05-26 | 1992-06-23 | Ibm Corporation | Control of pipelined operation in a microcomputer system employing dynamic bus sizing with 80386 processor and 82385 cache controller |
US5040109A (en) * | 1988-07-20 | 1991-08-13 | Digital Equipment Corporation | Efficient protocol for communicating between asychronous devices |
US5060239A (en) * | 1989-05-12 | 1991-10-22 | Alcatel Na Network Systems Corp. | Transfer strobe time delay selector and method for performing same |
-
1990
- 1990-08-24 CA CA002023998A patent/CA2023998A1/en not_active Abandoned
- 1990-10-12 JP JP2275077A patent/JPH077377B2/ja not_active Expired - Fee Related
- 1990-10-15 AU AU64641/90A patent/AU640695B2/en not_active Ceased
- 1990-10-24 NZ NZ235802A patent/NZ235802A/en unknown
- 1990-10-29 TW TW079109130A patent/TW230244B/zh active
- 1990-10-30 EP EP90311893A patent/EP0428293B1/en not_active Expired - Lifetime
- 1990-10-30 DE DE69031206T patent/DE69031206T2/de not_active Expired - Fee Related
- 1990-10-30 MY MYPI90001897A patent/MY107731A/en unknown
- 1990-10-30 SG SG1996000469A patent/SG43746A1/en unknown
- 1990-11-09 KR KR1019900018084A patent/KR940005346B1/ko not_active IP Right Cessation
- 1990-11-09 CN CN90109036A patent/CN1020812C/zh not_active Expired - Fee Related
- 1990-11-12 NO NO90904908A patent/NO904908L/no unknown
- 1990-11-12 PT PT95850A patent/PT95850A/pt not_active Application Discontinuation
- 1990-11-13 FI FI905611A patent/FI905611A0/fi not_active Application Discontinuation
-
1993
- 1993-08-24 US US08/111,034 patent/US5388250A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
FI905611A0 (fi) | 1990-11-13 |
MY107731A (en) | 1996-05-30 |
US5388250A (en) | 1995-02-07 |
EP0428293A2 (en) | 1991-05-22 |
CA2023998A1 (en) | 1991-05-14 |
TW230244B (no) | 1994-09-11 |
AU6464190A (en) | 1991-05-16 |
EP0428293B1 (en) | 1997-08-06 |
SG43746A1 (en) | 1997-11-14 |
NZ235802A (en) | 1994-02-25 |
CN1020812C (zh) | 1993-05-19 |
KR910010302A (ko) | 1991-06-29 |
AU640695B2 (en) | 1993-09-02 |
DE69031206T2 (de) | 1998-02-12 |
JPH03160548A (ja) | 1991-07-10 |
KR940005346B1 (ko) | 1994-06-17 |
EP0428293A3 (en) | 1992-02-19 |
CN1051801A (zh) | 1991-05-29 |
NO904908D0 (no) | 1990-11-12 |
DE69031206D1 (de) | 1997-09-11 |
JPH077377B2 (ja) | 1995-01-30 |
PT95850A (pt) | 1992-07-31 |
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