AU640695B2 - Apparatus and method for guaranteeing strobe separation timing - Google Patents

Apparatus and method for guaranteeing strobe separation timing Download PDF

Info

Publication number
AU640695B2
AU640695B2 AU64641/90A AU6464190A AU640695B2 AU 640695 B2 AU640695 B2 AU 640695B2 AU 64641/90 A AU64641/90 A AU 64641/90A AU 6464190 A AU6464190 A AU 6464190A AU 640695 B2 AU640695 B2 AU 640695B2
Authority
AU
Australia
Prior art keywords
read
signal
peripheral device
time period
write signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
AU64641/90A
Other languages
English (en)
Other versions
AU6464190A (en
Inventor
Thomas Francis Lewis
Stephen Patrick Thompson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of AU6464190A publication Critical patent/AU6464190A/en
Application granted granted Critical
Publication of AU640695B2 publication Critical patent/AU640695B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/4226—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Information Transfer Systems (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Communication Control (AREA)
AU64641/90A 1989-11-13 1990-10-15 Apparatus and method for guaranteeing strobe separation timing Ceased AU640695B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US43705989A 1989-11-13 1989-11-13
US437059 1989-11-13

Publications (2)

Publication Number Publication Date
AU6464190A AU6464190A (en) 1991-05-16
AU640695B2 true AU640695B2 (en) 1993-09-02

Family

ID=23734893

Family Applications (1)

Application Number Title Priority Date Filing Date
AU64641/90A Ceased AU640695B2 (en) 1989-11-13 1990-10-15 Apparatus and method for guaranteeing strobe separation timing

Country Status (15)

Country Link
US (1) US5388250A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0428293B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPH077377B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
KR (1) KR940005346B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CN (1) CN1020812C (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
AU (1) AU640695B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CA (1) CA2023998A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE69031206T2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
FI (1) FI905611A7 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
MY (1) MY107731A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
NO (1) NO904908L (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
NZ (1) NZ235802A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
PT (1) PT95850A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
SG (1) SG43746A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
TW (1) TW230244B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5481675A (en) * 1992-05-12 1996-01-02 International Business Machines Corporation Asynchronous serial communication system for delaying with software dwell time a receiving computer's acknowledgement in order for the transmitting computer to see the acknowledgement
KR950008661B1 (ko) * 1993-05-20 1995-08-04 현대전자산업주식회사 버스 다중화 회로
US5537582A (en) * 1993-05-21 1996-07-16 Draeger; Jeffrey S. Bus interface circuitry for synchronizing central processors running at multiple clock frequencies to other computer system circuitry
US5553275A (en) * 1993-07-13 1996-09-03 Intel Corporation Method and apparatus for synchronously detecting phase relationships between a high-frequency clock and a low-frequency clock
JP2551338B2 (ja) * 1993-07-23 1996-11-06 日本電気株式会社 情報処理装置
US5821784A (en) * 1995-12-29 1998-10-13 Intel Corporation Method and apparatus for generating 2/N mode bus clock signals
US5802132A (en) * 1995-12-29 1998-09-01 Intel Corporation Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme
US5834956A (en) * 1995-12-29 1998-11-10 Intel Corporation Core clock correction in a 2/N mode clocking scheme
US5826067A (en) * 1996-09-06 1998-10-20 Intel Corporation Method and apparatus for preventing logic glitches in a 2/n clocking scheme
US5862373A (en) * 1996-09-06 1999-01-19 Intel Corporation Pad cells for a 2/N mode clocking scheme
US5999995A (en) * 1996-12-27 1999-12-07 Oki Data Corporation Systems for adjusting a transfer rate between a host and a peripheral based on a calculation of the processing rate of the host
WO1999019805A1 (en) * 1997-10-10 1999-04-22 Rambus Incorporated Method and apparatus for two step memory write operations
US6401167B1 (en) 1997-10-10 2002-06-04 Rambus Incorporated High performance cost optimized memory
US6055587A (en) * 1998-03-27 2000-04-25 Adaptec, Inc, Integrated circuit SCSI I/O cell having signal assertion edge triggered timed glitch filter that defines a strobe masking period to protect the contents of data latches
US6087867A (en) * 1998-05-29 2000-07-11 Lsi Logic Corporation Transaction control circuit for synchronizing transactions across asynchronous clock domains
EP0978788A1 (en) * 1998-08-04 2000-02-09 Texas Instruments France Improvements in or relating to direct memory access data transfers
EP0978787A1 (en) * 1998-08-04 2000-02-09 Texas Instruments France Improvements in or relating to transferring data between asynchronous device
EP1175160B1 (en) * 1999-04-01 2003-10-08 Heeling Sports Limited Heeling apparatus and method
US6529570B1 (en) * 1999-09-30 2003-03-04 Silicon Graphics, Inc. Data synchronizer for a multiple rate clock source and method thereof
US7096377B2 (en) * 2002-03-27 2006-08-22 Intel Corporation Method and apparatus for setting timing parameters
US20070121398A1 (en) * 2005-11-29 2007-05-31 Bellows Mark D Memory controller capable of handling precharge-to-precharge restrictions
TWI506443B (zh) * 2012-12-27 2015-11-01 Mediatek Inc 處理器與週邊裝置之間的媒介週邊介面及其通信方法
CN109298248B (zh) * 2018-11-12 2020-12-01 中电科仪器仪表有限公司 一种基于fpga的复杂脉冲调制序列测量电路及方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0242879A2 (en) * 1986-04-23 1987-10-28 Nec Corporation Data processor with wait control allowing high speed access
WO1988002888A1 (en) * 1986-10-17 1988-04-21 Fujitsu Limited Data transfer system having transfer discrimination circuit

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3587044A (en) * 1969-07-14 1971-06-22 Ibm Digital communication system
US3623017A (en) * 1969-10-22 1971-11-23 Sperry Rand Corp Dual clocking arrangement for a digital computer
US4050096A (en) * 1974-10-30 1977-09-20 Motorola, Inc. Pulse expanding system for microprocessor systems with slow memory
US4050097A (en) * 1976-09-27 1977-09-20 Honeywell Information Systems, Inc. Synchronization technique for data transfers over an asynchronous common bus network coupling data processing apparatus
US4144562A (en) * 1977-06-23 1979-03-13 Ncr Corporation System and method for increasing microprocessor output data rate
US4143418A (en) * 1977-09-21 1979-03-06 Sperry Rand Corporation Control device and method for reading a data character from a computer at a fast rate and transmitting the character at a slow rate on a communication line
US4164787A (en) * 1977-11-09 1979-08-14 Bell Telephone Laboratories, Incorporated Multiple microprocessor intercommunication arrangement
DE2812242C2 (de) * 1978-03-21 1987-01-15 Robert Bosch Gmbh, 7000 Stuttgart Verfahren zur Ablaufsteuerung
US4262331A (en) * 1978-10-30 1981-04-14 Ibm Corporation Self-adaptive computer load control
US4539635A (en) * 1980-02-11 1985-09-03 At&T Bell Laboratories Pipelined digital processor arranged for conditional operation
US4494196A (en) * 1981-05-19 1985-01-15 Wang Laboratories, Inc. Controller for peripheral data storage units
US4476527A (en) * 1981-12-10 1984-10-09 Data General Corporation Synchronous data bus with automatically variable data rate
US4517641A (en) * 1982-04-30 1985-05-14 International Business Machines Corporation Lookahead I/O device control subsystem
US4807109A (en) * 1983-11-25 1989-02-21 Intel Corporation High speed synchronous/asynchronous local bus and data transfer method
JPS61255392A (ja) * 1985-05-09 1986-11-13 横河電機株式会社 カラ−画像表示装置
FR2586118B1 (fr) * 1985-08-06 1990-01-05 Bull Sems Procede d'echange de donnees entre un microprocesseur et une memoire et dispositif permettant la mise en oeuvre du procede
JPS6243764A (ja) * 1985-08-21 1987-02-25 Nec Corp バス・ステ−ト制御回路
JP2520872B2 (ja) * 1985-12-10 1996-07-31 オリンパス光学工業株式会社 画像表示装置
US4769632A (en) * 1986-02-10 1988-09-06 Inmos Limited Color graphics control system
US4888684A (en) * 1986-03-28 1989-12-19 Tandem Computers Incorporated Multiprocessor bus protocol
JPS6354655A (ja) * 1986-08-25 1988-03-09 Hitachi Ltd バスタイミング制御回路
JPS63155340A (ja) * 1986-12-19 1988-06-28 Fujitsu Ltd 記憶装置の読出し方式
US4851995A (en) * 1987-06-19 1989-07-25 International Business Machines Corporation Programmable variable-cycle clock circuit for skew-tolerant array processor architecture
US5151986A (en) * 1987-08-27 1992-09-29 Motorola, Inc. Microcomputer with on-board chip selects and programmable bus stretching
US5125084A (en) * 1988-05-26 1992-06-23 Ibm Corporation Control of pipelined operation in a microcomputer system employing dynamic bus sizing with 80386 processor and 82385 cache controller
US5040109A (en) * 1988-07-20 1991-08-13 Digital Equipment Corporation Efficient protocol for communicating between asychronous devices
US5060239A (en) * 1989-05-12 1991-10-22 Alcatel Na Network Systems Corp. Transfer strobe time delay selector and method for performing same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0242879A2 (en) * 1986-04-23 1987-10-28 Nec Corporation Data processor with wait control allowing high speed access
WO1988002888A1 (en) * 1986-10-17 1988-04-21 Fujitsu Limited Data transfer system having transfer discrimination circuit

Also Published As

Publication number Publication date
NO904908L (no) 1991-05-14
NO904908D0 (no) 1990-11-12
CN1020812C (zh) 1993-05-19
KR910010302A (ko) 1991-06-29
JPH03160548A (ja) 1991-07-10
EP0428293B1 (en) 1997-08-06
MY107731A (en) 1996-05-30
EP0428293A2 (en) 1991-05-22
DE69031206D1 (de) 1997-09-11
AU6464190A (en) 1991-05-16
TW230244B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1994-09-11
JPH077377B2 (ja) 1995-01-30
KR940005346B1 (ko) 1994-06-17
CN1051801A (zh) 1991-05-29
SG43746A1 (en) 1997-11-14
FI905611A0 (fi) 1990-11-13
CA2023998A1 (en) 1991-05-14
US5388250A (en) 1995-02-07
FI905611A7 (fi) 1991-05-14
PT95850A (pt) 1992-07-31
NZ235802A (en) 1994-02-25
DE69031206T2 (de) 1998-02-12
EP0428293A3 (en) 1992-02-19

Similar Documents

Publication Publication Date Title
AU640695B2 (en) Apparatus and method for guaranteeing strobe separation timing
US4368514A (en) Multi-processor system
US4860244A (en) Buffer system for input/output portion of digital data processing system
KR930005800B1 (ko) 데이타 처리시스템
US4271466A (en) Direct memory access control system with byte/word control of data bus
US5333294A (en) Configurable data width direct memory access device with a read address counter and a write address counter which increments the addresses based on the desired data transfer width
EP0006472B1 (en) Microcontroller for controlling bidirectional transfer of data between a central control unit and a plurality of external units
EP0426329A1 (en) Combined synchronous and asynchronous memory controller
US4462028A (en) Access control logic for video terminal display memory
US4316244A (en) Memory apparatus for digital computer system
US4665482A (en) Data multiplex control facility
US4462073A (en) Apparatus for fetching and decoding instructions
US4646259A (en) Strip map memory controller
KR100288177B1 (ko) 메모리 액세스 제어 회로
US4747074A (en) Display controller for detecting predetermined drawing command among a plurality of drawing commands
JPH03206543A (ja) 同期化回路
US5657055A (en) Method and apparatus for reading ahead display data into a display FIFO of a graphics controller
US5093902A (en) Memory control apparatus for accessing an image memory in cycle stealing fashion to read and write videotex signals
US4447877A (en) Memory bus interface system
US6189082B1 (en) Burst access of registers at non-consecutive addresses using a mapping control word
EP0939374A2 (en) Processor for information processing equipment and control method
US4384285A (en) Data character video display system with visual attributes
KR920002023B1 (ko) 데이타 처리 시스템
JPS6141433B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
US5088035A (en) System for accelerating execution of program instructions by a microprocessor