KR930703699A - 패턴된 평면화 표면을 갖는 멀티칩 모듈 및 집적회로기판 - Google Patents
패턴된 평면화 표면을 갖는 멀티칩 모듈 및 집적회로기판Info
- Publication number
- KR930703699A KR930703699A KR1019930702379A KR930702379A KR930703699A KR 930703699 A KR930703699 A KR 930703699A KR 1019930702379 A KR1019930702379 A KR 1019930702379A KR 930702379 A KR930702379 A KR 930702379A KR 930703699 A KR930703699 A KR 930703699A
- Authority
- KR
- South Korea
- Prior art keywords
- conductor layer
- shape
- conductor
- substrate
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
- H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/465—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer having channels for the next circuit layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/467—Adding a circuit layer by thin film methods
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/062—Manufacture or treatment of conductive parts of the interconnections by smoothing of conductive parts, e.g. by planarisation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0376—Flush conductors, i.e. flush with the surface of the printed circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0041—Etching of the substrate by chemical or physical means by plasma etching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
- H05K3/064—Photoresists
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
- H05K3/16—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation by cathodic sputtering
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/654,880 US5187119A (en) | 1991-02-11 | 1991-02-11 | Multichip module and integrated circuit substrates having planarized patterned surfaces |
| US654,880 | 1991-02-11 | ||
| PCT/US1992/001140 WO1992014261A1 (en) | 1991-02-11 | 1992-02-10 | Multichip module and integrated circuit substrates having planarized patterned surfaces |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR930703699A true KR930703699A (ko) | 1993-11-30 |
Family
ID=24626612
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019930702379A Withdrawn KR930703699A (ko) | 1991-02-11 | 1992-02-10 | 패턴된 평면화 표면을 갖는 멀티칩 모듈 및 집적회로기판 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US5187119A (enExample) |
| EP (1) | EP0571547A1 (enExample) |
| JP (1) | JPH06505833A (enExample) |
| KR (1) | KR930703699A (enExample) |
| CN (1) | CN1029274C (enExample) |
| CA (1) | CA2101426A1 (enExample) |
| TW (1) | TW226052B (enExample) |
| WO (1) | WO1992014261A1 (enExample) |
Families Citing this family (49)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5391516A (en) * | 1991-10-10 | 1995-02-21 | Martin Marietta Corp. | Method for enhancement of semiconductor device contact pads |
| US5300813A (en) * | 1992-02-26 | 1994-04-05 | International Business Machines Corporation | Refractory metal capped low resistivity metal conductor lines and vias |
| US5384281A (en) * | 1992-12-29 | 1995-01-24 | International Business Machines Corporation | Non-conformal and oxidizable etch stops for submicron features |
| US5397741A (en) * | 1993-03-29 | 1995-03-14 | International Business Machines Corporation | Process for metallized vias in polyimide |
| JP2947054B2 (ja) * | 1994-03-04 | 1999-09-13 | ヤマハ株式会社 | 配線形成法 |
| US5494854A (en) * | 1994-08-17 | 1996-02-27 | Texas Instruments Incorporated | Enhancement in throughput and planarity during CMP using a dielectric stack containing HDP-SiO2 films |
| KR0171069B1 (ko) * | 1994-10-27 | 1999-03-30 | 문정환 | 반도체 장치의 접촉부 형성방법 |
| US5851899A (en) * | 1996-08-08 | 1998-12-22 | Siemens Aktiengesellschaft | Gapfill and planarization process for shallow trench isolation |
| JPH10163319A (ja) * | 1996-11-29 | 1998-06-19 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
| US6127721A (en) * | 1997-09-30 | 2000-10-03 | Siemens Aktiengesellschaft | Soft passivation layer in semiconductor fabrication |
| US6706623B1 (en) * | 1997-12-10 | 2004-03-16 | Texas Instruments Incorporated | Method and system for avoiding plasma etch damage |
| US6093656A (en) * | 1998-02-26 | 2000-07-25 | Vlsi Technology, Inc. | Method of minimizing dishing during chemical mechanical polishing of semiconductor metals for making a semiconductor device |
| TW407342B (en) * | 1998-06-17 | 2000-10-01 | United Microelectronics Corp | Planarization method of damascene structure |
| US6150256A (en) * | 1998-10-30 | 2000-11-21 | International Business Machines Corporation | Method for forming self-aligned features |
| US6225210B1 (en) * | 1998-12-09 | 2001-05-01 | Advanced Micro Devices, Inc. | High density capping layers with improved adhesion to copper interconnects |
| JP3708732B2 (ja) * | 1998-12-25 | 2005-10-19 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
| US6803327B1 (en) | 1999-04-05 | 2004-10-12 | Taiwan Semiconductor Manufacturing Company | Cost effective polymide process to solve passivation extrusion or damage and SOG delminates |
| US6358119B1 (en) | 1999-06-21 | 2002-03-19 | Taiwan Semiconductor Manufacturing Company | Way to remove CU line damage after CU CMP |
| US6800548B2 (en) * | 2002-01-02 | 2004-10-05 | Intel Corporation | Method to avoid via poisoning in dual damascene process |
| CN1176488C (zh) * | 2002-03-15 | 2004-11-17 | 台湾积体电路制造股份有限公司 | 测试金属层间介电层强度的方法 |
| JP2005191408A (ja) * | 2003-12-26 | 2005-07-14 | Matsushita Electric Ind Co Ltd | コイル導電体とその製造方法およびこれを用いた電子部品 |
| US7426780B2 (en) | 2004-11-10 | 2008-09-23 | Enpirion, Inc. | Method of manufacturing a power module |
| US7462317B2 (en) | 2004-11-10 | 2008-12-09 | Enpirion, Inc. | Method of manufacturing an encapsulated package for a magnetic device |
| JP4578254B2 (ja) * | 2005-01-26 | 2010-11-10 | 京セラ株式会社 | 多層配線基板 |
| US8631560B2 (en) * | 2005-10-05 | 2014-01-21 | Enpirion, Inc. | Method of forming a magnetic device having a conductive clip |
| US8701272B2 (en) * | 2005-10-05 | 2014-04-22 | Enpirion, Inc. | Method of forming a power module with a magnetic device having a conductive clip |
| US8139362B2 (en) * | 2005-10-05 | 2012-03-20 | Enpirion, Inc. | Power module with a magnetic device having a conductive clip |
| US7688172B2 (en) * | 2005-10-05 | 2010-03-30 | Enpirion, Inc. | Magnetic device having a conductive clip |
| US20070138405A1 (en) * | 2005-12-16 | 2007-06-21 | 3M Innovative Properties Company | Corona etching |
| US7920042B2 (en) * | 2007-09-10 | 2011-04-05 | Enpirion, Inc. | Micromagnetic device and method of forming the same |
| US8018315B2 (en) * | 2007-09-10 | 2011-09-13 | Enpirion, Inc. | Power converter employing a micromagnetic device |
| US8133529B2 (en) * | 2007-09-10 | 2012-03-13 | Enpirion, Inc. | Method of forming a micromagnetic device |
| US7955868B2 (en) * | 2007-09-10 | 2011-06-07 | Enpirion, Inc. | Method of forming a micromagnetic device |
| US7952459B2 (en) * | 2007-09-10 | 2011-05-31 | Enpirion, Inc. | Micromagnetic device and method of forming the same |
| US8692532B2 (en) | 2008-04-16 | 2014-04-08 | Enpirion, Inc. | Power converter with controller operable in selected modes of operation |
| US8686698B2 (en) * | 2008-04-16 | 2014-04-01 | Enpirion, Inc. | Power converter with controller operable in selected modes of operation |
| US9246390B2 (en) * | 2008-04-16 | 2016-01-26 | Enpirion, Inc. | Power converter with controller operable in selected modes of operation |
| US8541991B2 (en) | 2008-04-16 | 2013-09-24 | Enpirion, Inc. | Power converter with controller operable in selected modes of operation |
| US8153473B2 (en) * | 2008-10-02 | 2012-04-10 | Empirion, Inc. | Module having a stacked passive element and method of forming the same |
| US8266793B2 (en) * | 2008-10-02 | 2012-09-18 | Enpirion, Inc. | Module having a stacked magnetic device and semiconductor device and method of forming the same |
| US8339802B2 (en) * | 2008-10-02 | 2012-12-25 | Enpirion, Inc. | Module having a stacked magnetic device and semiconductor device and method of forming the same |
| US9054086B2 (en) * | 2008-10-02 | 2015-06-09 | Enpirion, Inc. | Module having a stacked passive element and method of forming the same |
| US9548714B2 (en) * | 2008-12-29 | 2017-01-17 | Altera Corporation | Power converter with a dynamically configurable controller and output filter |
| US8698463B2 (en) * | 2008-12-29 | 2014-04-15 | Enpirion, Inc. | Power converter with a dynamically configurable controller based on a power conversion mode |
| US8867295B2 (en) | 2010-12-17 | 2014-10-21 | Enpirion, Inc. | Power converter for a memory module |
| EP2602818A1 (en) * | 2011-12-09 | 2013-06-12 | Ipdia | An interposer device |
| US9509217B2 (en) | 2015-04-20 | 2016-11-29 | Altera Corporation | Asymmetric power flow controller for a power converter and method of operating the same |
| CN112533395B (zh) * | 2020-12-21 | 2021-12-24 | 北京同方信息安全技术股份有限公司 | 印制电路板中埋入电阻的方法及其印制电路板 |
| CN114190002A (zh) * | 2021-12-09 | 2022-03-15 | 上达电子(深圳)股份有限公司 | 一种柔性封装基板半埋入式厚铜精细线路的成型方法 |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57145340A (en) * | 1981-03-05 | 1982-09-08 | Toshiba Corp | Manufacture of semiconductor device |
| US4415606A (en) * | 1983-01-10 | 1983-11-15 | Ncr Corporation | Method of reworking upper metal in multilayer metal integrated circuits |
| US4617193A (en) * | 1983-06-16 | 1986-10-14 | Digital Equipment Corporation | Planar interconnect for integrated circuits |
| US4584761A (en) * | 1984-05-15 | 1986-04-29 | Digital Equipment Corporation | Integrated circuit chip processing techniques and integrated chip produced thereby |
| JPS6140134A (ja) * | 1984-08-01 | 1986-02-26 | Tokyo Ink Kk | シ−トによるホツトメルト被覆方法 |
| JPS61140134A (ja) * | 1984-12-13 | 1986-06-27 | Toshiba Corp | 半導体装置の製造方法 |
| JPS63215056A (ja) * | 1987-03-04 | 1988-09-07 | Matsushita Electronics Corp | 半導体装置の製造方法 |
| JPH0821559B2 (ja) * | 1988-02-12 | 1996-03-04 | 三菱電機株式会社 | 半導体集積回路装置の製造方法 |
| US5055425A (en) * | 1989-06-01 | 1991-10-08 | Hewlett-Packard Company | Stacked solid via formation in integrated circuit systems |
| US4952275A (en) * | 1989-12-15 | 1990-08-28 | Microelectronics And Computer Technology Corporation | Copper etching solution and method |
-
1991
- 1991-02-11 US US07/654,880 patent/US5187119A/en not_active Expired - Lifetime
-
1992
- 1992-02-10 KR KR1019930702379A patent/KR930703699A/ko not_active Withdrawn
- 1992-02-10 EP EP92907235A patent/EP0571547A1/en not_active Withdrawn
- 1992-02-10 CA CA002101426A patent/CA2101426A1/en not_active Abandoned
- 1992-02-10 WO PCT/US1992/001140 patent/WO1992014261A1/en not_active Ceased
- 1992-02-10 JP JP4507047A patent/JPH06505833A/ja active Pending
- 1992-02-11 TW TW081100926A patent/TW226052B/zh active
- 1992-02-11 CN CN92101596A patent/CN1029274C/zh not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1029274C (zh) | 1995-07-05 |
| JPH06505833A (ja) | 1994-06-30 |
| TW226052B (enExample) | 1994-07-01 |
| CA2101426A1 (en) | 1992-08-12 |
| US5187119A (en) | 1993-02-16 |
| CN1070287A (zh) | 1993-03-24 |
| EP0571547A1 (en) | 1993-12-01 |
| EP0571547A4 (enExample) | 1994-02-09 |
| WO1992014261A1 (en) | 1992-08-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0105 | International application |
St.27 status event code: A-0-1-A10-A15-nap-PA0105 |
|
| R17-X000 | Change to representative recorded |
St.27 status event code: A-3-3-R10-R17-oth-X000 |
|
| PG1501 | Laying open of application |
St.27 status event code: A-1-1-Q10-Q12-nap-PG1501 |
|
| PC1203 | Withdrawal of no request for examination |
St.27 status event code: N-1-6-B10-B12-nap-PC1203 |
|
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid | ||
| R18-X000 | Changes to party contact information recorded |
St.27 status event code: A-3-3-R10-R18-oth-X000 |
|
| P22-X000 | Classification modified |
St.27 status event code: A-2-2-P10-P22-nap-X000 |