KR930024165A - 반도체 장치 및 그 제조 방법 - Google Patents

반도체 장치 및 그 제조 방법 Download PDF

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Publication number
KR930024165A
KR930024165A KR1019930007566A KR930007566A KR930024165A KR 930024165 A KR930024165 A KR 930024165A KR 1019930007566 A KR1019930007566 A KR 1019930007566A KR 930007566 A KR930007566 A KR 930007566A KR 930024165 A KR930024165 A KR 930024165A
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South Korea
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semiconductor substrate
type
semiconductor
single crystal
silicon substrate
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KR1019930007566A
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English (en)
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KR0131190B1 (ko
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고이치 기시
시즈오 사와다
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사또오 후미오
가부시기가이샤 도시바
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 메모리셀을 고집적으로 형성하는데 적합한 반도체 기판과 그 제조방법 및 고집적화된 반도체 기억장치를 제공하는 것을 목적으로 한다.
실리콘 산화막(12)이 선택적으로 형성된 P+형 실리콘 기판(11)과 N형 단결정 실리콘 기판(13)이 접착된다.
트렌치 커패시터는 실리콘 산화막(15) 및 N형 단결정 실리콘 기판(13)을 관통하여 P+형 실리콘 기판(11)내에 형성되며, 내부는 게이트 절연막(17), P형 폴리실리콘(18)으로 형성된다. PMOS 트랜지스터 확산영역의 P형 확산층(22)과 축적노드의 P형 폴리실리콘(18)과는 P형 확산층(21) 및 P형 에피택셜층(20)에 의해 전기적으로 접속된다. 또, 플레이트 전극 취출부분으로서 N형 단결정 실리콘 기판(13)에 N형 확산층(24)이 형성되어 있다.

Description

반도체 장치 및 그 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 의한 일 실시예에 있어서의 반도체 기억장치와 그 제조 공정을 도시하는 제1단면도, 제2도는 본 발명에 의한 일 실시예에 있어서의 반도체 기억장치와 그 제조 공정을 도시하는 제2단면도.

Claims (4)

  1. 제1반도체 기판(11, 30)과, 이 제1반도체 기판에 선택적으로 형성되는 동시에 평탄화된 절연막(12)과, 상기 제1반도체 기판상에 형성되는 단결정 반도체로 이루어지는 제2반도체 기판(13)을 갖는 것을 특징으로 하는 반도체 기판.
  2. 제1반도체 기판 표면을 선택적으로 산화시켜 절연막을 형성하는 공정과, 상기 제1반도체 기판 표면을 평탄화하는 공정과, 상기 제1반도체 기판 표면에 단결정 반도체로 이루어지는 제2반도체 기판을 접착하는 공정을 포함하는 반도체 기판의 제조방법.
  3. 제1반도체 기판 표면에 선택적으로 홈을 형성하는 공정과, 이 홈을 절연물로 채워 상기 제1반도체 기판 표면을 평탄화하는 공정과, 상기 제1반도체 기판 표면에 단결정 반도체로 이루어지는 제2반도체 기판을 접착하는 공정을 포함하는 반도체 기판의 제조 방법.
  4. 제1반도체 기판(11, 30)과, 이 제1반도체 기판에 선택적으로 형성된 절연막(12)과, 이 절연막을 통해 상기 제1반도체 기판상에 형성되는 단결정 반도체로 이루어지는 제2반도체 기판(13)을 갖는 반도체 기판을 사용한 1 트랜지스터·1 커패시터형의 반도체 기억장치로서, 상기 제2반도체 기판 및 상기 절연막을 관통하여 상기 제1반도체 기판내에 달하는 트렌치 커패시터를 가지며, 상기 제1반도체 기판을 이 트렌치 커패시터의 플레이트 전극으로 하는 것을 특징으로 하는 반도체 기억 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930007566A 1992-05-06 1993-05-03 반도체 장치 및 그 제조 방법 KR0131190B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP4113377A JP2796012B2 (ja) 1992-05-06 1992-05-06 半導体装置及びその製造方法
JP92-113377 1992-05-06

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KR930024165A true KR930024165A (ko) 1993-12-22
KR0131190B1 KR0131190B1 (ko) 1998-04-15

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US (1) US5302542A (ko)
JP (1) JP2796012B2 (ko)
KR (1) KR0131190B1 (ko)

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Publication number Priority date Publication date Assignee Title
JP3439493B2 (ja) * 1992-12-01 2003-08-25 沖電気工業株式会社 半導体記憶装置の製造方法
JP3272517B2 (ja) * 1993-12-01 2002-04-08 三菱電機株式会社 半導体装置の製造方法
JP2791260B2 (ja) * 1993-03-01 1998-08-27 株式会社東芝 半導体装置の製造方法
US5585284A (en) * 1993-07-02 1996-12-17 Hyundai Electronics Industries Co., Ltd. Method of manufacturing a SOI DRAM
US5396452A (en) * 1993-07-02 1995-03-07 Wahlstrom; Sven E. Dynamic random access memory
US6242772B1 (en) 1994-12-12 2001-06-05 Altera Corporation Multi-sided capacitor in an integrated circuit
US6737332B1 (en) * 2002-03-28 2004-05-18 Advanced Micro Devices, Inc. Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making same
FR2849962B1 (fr) * 2003-01-13 2005-09-30 St Microelectronics Sa Condensateur enterre associe a une cellule sram
JP4456027B2 (ja) * 2005-03-25 2010-04-28 Ｏｋｉセミコンダクタ株式会社 貫通導電体の製造方法
JP2006310576A (ja) 2005-04-28 2006-11-09 Renesas Technology Corp 半導体装置およびその製造方法
TWI696247B (zh) * 2019-01-28 2020-06-11 力晶積成電子製造股份有限公司 記憶體結構

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JPS594080A (ja) * 1982-06-30 1984-01-10 Toshiba Corp Ｍｏｓ型半導体装置及びその製造方法
DE3583183D1 (de) * 1984-05-09 1991-07-18 Toshiba Kawasaki Kk Verfahren zur herstellung eines halbleitersubstrates.
JPH0671043B2 (ja) * 1984-08-31 1994-09-07 株式会社東芝 シリコン結晶体構造の製造方法
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JPH0797625B2 (ja) * 1986-11-19 1995-10-18 三菱電機株式会社 半導体記憶装置
JPH0795568B2 (ja) * 1987-04-27 1995-10-11 日本電気株式会社 半導体記憶装置
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Publication number Publication date
US5302542A (en) 1994-04-12
JPH05315564A (ja) 1993-11-26
JP2796012B2 (ja) 1998-09-10
KR0131190B1 (ko) 1998-04-15

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