KR970067908A - 반도체 집적회로장치 및 그 제조방법 및 논리회로 - Google Patents

반도체 집적회로장치 및 그 제조방법 및 논리회로 Download PDF

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KR970067908A
KR970067908A KR1019960058226A KR19960058226A KR970067908A KR 970067908 A KR970067908 A KR 970067908A KR 1019960058226 A KR1019960058226 A KR 1019960058226A KR 19960058226 A KR19960058226 A KR 19960058226A KR 970067908 A KR970067908 A KR 970067908A
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gate electrode
semiconductor layer
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gate
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히로유키 모리나카
카미오 우에다
코이치로 마시코
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기다오까 다까시
미쓰비시 뎅끼 가부시끼가이샤
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Abstract

집적도를 손상하는 일없이 트랜지스터의 내압의 열화를 방지할 수 있는 SOI 구조의 반도체 집적회로장치 및 그 제조방법을 얻는다. 매립산화막은 P층 실리콘층의 전체면상에 형성되지 않지만, 게이트전극의 아래쪽에 위치하는 영역에 개구부를 갖는다. 이 개구부를 충전하여 관통 P층(9)이 형성된다. 따라서, SOI층(3)과 P형 실리콘층(1)은 관통 P층(9)을 통해 전기적으로 접속된다. 또, 게이트 전극(7)과 관통 P층(9)과의 평면위치 및 형성이 합치한다.

Description

반도체 집적회로장치 및 그 제조방법 및 논리회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 실시의 형태 1인 N형의 SOI 트랜지스터의 구조를 나타내는 단면도

Claims (3)

  1. 기판과; 상기 기판상에 형성되는 절연층과; 상기 절연층상에 형성되는 제1의 도전형의 반도체층과; 상기 반도체층의 표면에 선택적으로 형성되는 제2의 도전형의 제1 및 제2의 반도체 영역과; 상기 제1 및 제2의 반도체 영역간의 상기 반도체층상에 형성되는 게이트 절연막과; 상기 게이트 절연막상에 형성되는 게이트전극을 구비하고, 상기 게이트전극 아래의 상기 반도체층의 표면이 채널영역으로 규정되고, 상기 게이트 전극, 상기 게이트 절연막, 상기 제1 및 제2의 반도체 영역 및 상기 채널영역에 의해 제2의 도전형의 트랜지스터가 형성되며; 상기 절연층은 상기 게이트전극의 아래쪽에 위치한 영역에 상기 채널영역에 축적된 캐리어를 상기 채널영역이외의 영역에 방출할 수 있는 캐리어 방출 가능 영역을 가지는 것을 특징으로 하는 반도체 집적회로장치.
  2. 기판과; 상기 기판상에 형성되고 개구부를 가지는 절연층과; 상기 개구부를 충전하여 형성되는 관통반도체층과; 상기 관총반도체층을 함유하는 상기 절연층상에 형성되는 제1의 도전형의 반도체층과; 상기 반도체층상에의 표면에 선택적으로 형성되는 제2의 도전형의 제1 및 제2의 반도체 영역과; 상기 제1 및 제2의 반도체 영역간의 상기 반도체층상에 형성되는 게이트 절연막과; 상기 게이트 절연막상에 형성되는 게이트전극을 구비하고, 상기 게이트전극 아래의 상기 제3의 반도체층의 표면이 채널영역으로 규정되고, 상기 게이트 전극, 상기 게이트 절연막, 상기 제1 및 제2의 반도체 영역 및 상기 채널영역에 의해 제2의 도전형의 트랜지스터가 형성되며; 상기 게이트 전극과 상기 관통반도체층과의 평면위치 및 형상이 합치하는 것을 특징으로 하는 반도체 집적회로장치.
  3. (a) 기판을 준비하는 스텝과; (b) 상기 기판상에 터널현상이 생기는 정도의 막 두께를 가지는 제1의 부분 절연층을 형성하는 스텝과; (c) 상기 제1의 부분 절연층상에 제1의 도전형의 캐리어 축적층을 형성하는 스텝과; (d) 상기 캐리어 축적층을 덮고, 상기 제1의 부분 절연층상에 제2의 부분절연일층을 형성하는 스텝을 구비하고, 상기 제1,및 제2 부분 절연층은 일체화되어 하나의 절연층을 형성하고, 상기 캐리어 축적층상의 상기 절연층의 막 두께는 터널현상이 생기는 정도로 설정되며, (e) 상기 절연층상에 제1의 도전형의 반도체층을 형성하는 스텝과; (f) 상기 반도체층상에 게이트 절연막을 통해 게이트 전극을 형성하는 스텝을 더 구비하고, 상기 게이트 전극 아래의 상기 반도체층의 표면은 채널영역으로서 규정되고, 상기 게이트 전극 아래에 상기 캐리어 측적층이 위치하고, (g) 상기 게이트 전극을 마스크로서 사용하여 상기 반도체층에 대하여 제2의 도전형의 불순물을 도입하여 상기 반도체층의 표면에 제2의 도전형의 제1 및 제2의 반도체 영역을 형성하는 스텝을 더 구비하고, 상기 게이트 전극, 상기 게이트 절연막, 상기 제1 및 제2의 반도체 영역 및 상기 채널영역에 의해 제2의 도전형의 트랜지스터를 형성하는 것을 특징으로 하는 반도체 집적회로장치의 제조방법.
KR1019960058226A 1996-03-18 1996-11-27 반도체집적회로장치및그제조방법및논리회로 KR100252479B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP8060795A JPH09252139A (ja) 1996-03-18 1996-03-18 半導体集積回路装置及びその製造方法並びに論理回路
JP96-060795 1996-03-18
JP96060795 1996-03-18

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KR100230799B1 (ko) * 1996-09-13 1999-11-15 김영환 절연막 터널링 트랜지스터의 제조방법
JPH10275914A (ja) * 1997-03-31 1998-10-13 Nec Corp 半導体装置
US6759282B2 (en) * 2001-06-12 2004-07-06 International Business Machines Corporation Method and structure for buried circuits and devices
JP5122818B2 (ja) * 2004-09-17 2013-01-16 シャープ株式会社 薄膜半導体装置の製造方法
US9379028B2 (en) * 2009-11-16 2016-06-28 Globalfoundries Inc. SOI CMOS structure having programmable floating backplate
CN104716091B (zh) * 2013-12-13 2018-07-24 昆山国显光电有限公司 阵列基板的制备方法、阵列基板和有机发光显示器件
CN105097711B (zh) * 2014-05-04 2018-03-30 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
CN105470257A (zh) * 2014-06-18 2016-04-06 上海华力微电子有限公司 一种闪存器件
CN112289852B (zh) * 2020-12-15 2021-05-11 北京芯可鉴科技有限公司 降低埋氧层泄漏电流的soi器件结构及其制作方法

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US5604368A (en) * 1994-07-15 1997-02-18 International Business Machines Corporation Self-aligned double-gate MOSFET by selective lateral epitaxy
US5497019A (en) * 1994-09-22 1996-03-05 The Aerospace Corporation Silicon-on-insulator gate-all-around MOSFET devices and fabrication methods

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CN1110099C (zh) 2003-05-28
KR100252479B1 (ko) 2000-04-15
CN1160291A (zh) 1997-09-24
JPH09252139A (ja) 1997-09-22

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