KR930014854A - 와이어 본딩 패드 형성방법 - Google Patents

와이어 본딩 패드 형성방법 Download PDF

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Publication number
KR930014854A
KR930014854A KR1019910022980A KR910022980A KR930014854A KR 930014854 A KR930014854 A KR 930014854A KR 1019910022980 A KR1019910022980 A KR 1019910022980A KR 910022980 A KR910022980 A KR 910022980A KR 930014854 A KR930014854 A KR 930014854A
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South Korea
Prior art keywords
polyimide
wire bonding
bonding pad
protective film
metal wiring
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Application number
KR1019910022980A
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English (en)
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KR940007290B1 (ko
Inventor
류호경
박계순
길명군
김광철
백인혁
Original Assignee
정몽헌
현대전자산업 주식회사
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Priority to KR1019910022980A priority Critical patent/KR940007290B1/ko
Publication of KR930014854A publication Critical patent/KR930014854A/ko
Application granted granted Critical
Publication of KR940007290B1 publication Critical patent/KR940007290B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음

Description

와이어 본딩 패드 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 집적회로칩을 나타낸 평면도.
제2a도 내지 제2c도는 제1도의 a-a' 부분을 절단한 종래의 와이어 본딩 패드 형성단계를 나타낸 단면도
제3a도 내지 제3d도는 제1도의 a-a' 부분을 절단한 본 발명의 실시예에 의한 와이어 본딩 패드 형성단계를 나타낸 단면도.
* 도면의 주요부분에 대한 부호의 설명
1 : 집적회로칩 2 : 집적회로부
3 : 와이어본딩패드 3A : 와이어본딩패드부
4 : 실리콘기판 5 : 금속층
5A : 금속배선 6 : 보호막
7 : 폴리이미드층 7A : 폴리이미드패턴
8 : 절연층 9 : 폴리이미드잔여물
10 : 패드영역

Claims (1)

  1. 실리콘 기판상에 금속배선을 형성한 집적회로 칩상에 전반적으로 보호막을 증착한 후, 상기 보호막을 예정부분 식각하여 금속배선을 노출시킨 다음, 보호막을 포함하는 전체 구조 상부에 전반적으로 감광성 폴리이미드를 코팅하는 단계와, 와이어 본딩 패드가 형성될 부분의 감광성 폴리이미드를 노광시키고, 노광된폴리이미드를 현상액으로 현상하여 금속배선 상부가 노출되는 와이어 본딩 패드를 형성하는 단계와, 상기감광성 폴리이미드를 고온에서 경화시키는 단계로 이루어지는 와이어 본딩 패드 형성방법에 있어서, 폴리이미드를 현상한 후에도 와이어 본딩 패드부에 남아 있는 폴리이미드 잔여물을 제거하기 의하여, 상기 감광성폴리이미드의 경화공정 후 O2플라즈마로 10 내지 60초간 폴리이미드 에치공정을 실시하는 것을 특정으로하는 와이어 본딩 패드 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910022980A 1991-12-14 1991-12-14 와이어 본딩 패드 형성방법 KR940007290B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910022980A KR940007290B1 (ko) 1991-12-14 1991-12-14 와이어 본딩 패드 형성방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910022980A KR940007290B1 (ko) 1991-12-14 1991-12-14 와이어 본딩 패드 형성방법

Publications (2)

Publication Number Publication Date
KR930014854A true KR930014854A (ko) 1993-07-23
KR940007290B1 KR940007290B1 (ko) 1994-08-12

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100437621B1 (ko) * 1996-10-30 2004-08-25 주식회사 하이닉스반도체 반도체소자의제조방법

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6495442B1 (en) 2000-10-18 2002-12-17 Magic Corporation Post passivation interconnection schemes on top of the IC chips

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100437621B1 (ko) * 1996-10-30 2004-08-25 주식회사 하이닉스반도체 반도체소자의제조방법

Also Published As

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KR940007290B1 (ko) 1994-08-12

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