KR920020506A - 램덤 액세스 메모리 - Google Patents
램덤 액세스 메모리 Download PDFInfo
- Publication number
- KR920020506A KR920020506A KR1019920005443A KR920005443A KR920020506A KR 920020506 A KR920020506 A KR 920020506A KR 1019920005443 A KR1019920005443 A KR 1019920005443A KR 920005443 A KR920005443 A KR 920005443A KR 920020506 A KR920020506 A KR 920020506A
- Authority
- KR
- South Korea
- Prior art keywords
- memory
- random access
- precharge
- array group
- access memory
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Databases & Information Systems (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 이 발명은 한 실시예에 의한 램덤 액세스 메모리의 메모리 어레이 주변의 구성을 표시한 회로도.
Claims (2)
- 많이 분활된 메모리 어레이군보다 구성된 메모리부가 있어 액세스 요구시에 상기 메모리 어레이군의 1부를 활성화하여, 해당 메모리 어레이에 기억된 정보를 비트선대에 읽어내기 증폭기로 증폭하여, 이것을 신호선이 공통으로 접속된 각 메모리 어레이군마다의 스윗징 수단을 통해서 데이터선에 전송하도록 한 랜덤 액세스 메모리에 있어서, 상기 비트선대 및 데이터선대를 제1의 전위에 프레챠-지하는 제1의 프레챠-지수단과, 상기 데이터선택들 제2의 전위에 프레챠-지하는 제2의 프레챠-지 수단과를 비치하여, 액세스 요구시에 활성화되는 메모리 어레이군에 속한 데이터선의 프레챠-지 전위와, 비활성인 메몰리 어레이군에 속한 데이터선의 프레챠-지 전위와를 다른 치로 설정하도록 한 특징이 있는 랜덤 액세스 메모리.
- 제1항에 있어서, 상기 제2의 전위로서 전원전압, 또는 전원전압보다도 제2의 프레챠-지 수단을 구성하는 트랜지스타의 한계치분 낮은 치를 사용하는 것이 특징으로 하는 랜덤 액세스 메모리.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP91-106789 | 1991-04-09 | ||
JP3106789A JP2781080B2 (ja) | 1991-04-09 | 1991-04-09 | ランダムアクセスメモリ |
Publications (2)
Publication Number | Publication Date |
---|---|
KR920020506A true KR920020506A (ko) | 1992-11-21 |
KR960009948B1 KR960009948B1 (ko) | 1996-07-25 |
Family
ID=14442668
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920005443A KR960009948B1 (ko) | 1991-04-09 | 1992-04-01 | 랜덤 액세스 메모리 |
Country Status (4)
Country | Link |
---|---|
US (2) | US5321657A (ko) |
JP (1) | JP2781080B2 (ko) |
KR (1) | KR960009948B1 (ko) |
DE (1) | DE4211843C2 (ko) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR940001644B1 (ko) * | 1991-05-24 | 1994-02-28 | 삼성전자 주식회사 | 메모리 장치의 입출력 라인 프리차아지 방법 |
JP2697568B2 (ja) * | 1993-08-26 | 1998-01-14 | 日本電気株式会社 | 半導体記憶装置 |
JP3364810B2 (ja) * | 1993-09-14 | 2003-01-08 | 三菱電機株式会社 | 半導体記憶装置 |
JPH07272480A (ja) * | 1994-03-30 | 1995-10-20 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP3225813B2 (ja) * | 1995-11-20 | 2001-11-05 | 富士通株式会社 | 半導体記憶装置 |
US5710738A (en) * | 1996-12-17 | 1998-01-20 | Powerchip Semiconductor Corp. | Low power dynamic random access memory |
JP3720945B2 (ja) * | 1997-04-04 | 2005-11-30 | 株式会社東芝 | 半導体記憶装置 |
JP4827298B2 (ja) * | 2001-01-22 | 2011-11-30 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
KR100600047B1 (ko) * | 2004-05-06 | 2006-07-13 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
US11133044B2 (en) | 2018-06-01 | 2021-09-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interleaved routing for MRAM cell selection |
US11094361B2 (en) | 2018-09-05 | 2021-08-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transistorless memory cell |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2712735B1 (de) * | 1977-03-23 | 1978-09-14 | Ibm Deutschland | Lese-/Schreibzugriffschaltung zu Speicherzellen eines Speichers und Verfahren zu ihrem Betrieb |
JPH0664907B2 (ja) * | 1985-06-26 | 1994-08-22 | 株式会社日立製作所 | ダイナミツク型ram |
US4658381A (en) * | 1985-08-05 | 1987-04-14 | Motorola, Inc. | Bit line precharge on a column address change |
US4926384A (en) * | 1988-01-25 | 1990-05-15 | Visic, Incorporated | Static ram with write recovery in selected portion of memory array |
US4996671A (en) * | 1989-02-18 | 1991-02-26 | Sony Corporation | Semiconductor memory device |
JPH0814989B2 (ja) * | 1989-05-09 | 1996-02-14 | 日本電気株式会社 | 内部同期型スタティックram |
JP2825291B2 (ja) * | 1989-11-13 | 1998-11-18 | 株式会社東芝 | 半導体記憶装置 |
-
1991
- 1991-04-09 JP JP3106789A patent/JP2781080B2/ja not_active Expired - Lifetime
-
1992
- 1992-04-01 KR KR1019920005443A patent/KR960009948B1/ko not_active IP Right Cessation
- 1992-04-08 US US07/865,145 patent/US5321657A/en not_active Ceased
- 1992-04-08 DE DE4211843A patent/DE4211843C2/de not_active Expired - Lifetime
-
1996
- 1996-06-13 US US08/664,081 patent/USRE36027E/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2781080B2 (ja) | 1998-07-30 |
KR960009948B1 (ko) | 1996-07-25 |
DE4211843A1 (de) | 1992-10-15 |
JPH04310690A (ja) | 1992-11-02 |
US5321657A (en) | 1994-06-14 |
USRE36027E (en) | 1999-01-05 |
DE4211843C2 (de) | 1995-12-21 |
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Payment date: 20110617 Year of fee payment: 16 |
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