KR910020942A - 스택 커패시터 셀의 제조방법 - Google Patents

스택 커패시터 셀의 제조방법 Download PDF

Info

Publication number
KR910020942A
KR910020942A KR1019900006472A KR900006472A KR910020942A KR 910020942 A KR910020942 A KR 910020942A KR 1019900006472 A KR1019900006472 A KR 1019900006472A KR 900006472 A KR900006472 A KR 900006472A KR 910020942 A KR910020942 A KR 910020942A
Authority
KR
South Korea
Prior art keywords
polysilicon
insulating film
pad
manufacturing
capacitor cell
Prior art date
Application number
KR1019900006472A
Other languages
English (en)
Other versions
KR920008294B1 (ko
Inventor
전영권
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019900006472A priority Critical patent/KR920008294B1/ko
Priority to GB9109684A priority patent/GB2243951B/en
Priority to DE4114917A priority patent/DE4114917A1/de
Priority to JP3102593A priority patent/JPH0719849B2/ja
Publication of KR910020942A publication Critical patent/KR910020942A/ko
Application granted granted Critical
Publication of KR920008294B1 publication Critical patent/KR920008294B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음

Description

스택 커패시터 셀의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 제조공정을 나타낸 단면도.

Claims (1)

  1. 기판(1)위에 게이트 산화막(2), 게이트(3), 절연막(4)을 형성한 것에 있어서, 상기위에 피드 폴리 실리콘(5), 절연막(6)을 증착후 에칭하여 콘택트 패드를 형성하고, 산화성 분위기에서 열처리하여 폴리실리콘 패드 에지를 따라 실리콘 산화막이 형성되게 하며, 스토리지 노드 폴리 실리콘(7), 유전체(8), 플레이트폴리 실리콘(9)을 형성하여 스택 커패시터를 제호한 후 절연막(10)을 증착하고, 비트라인 콘택트를 오픈하여 패드 폴리실리콘(5)이 드러나게 하고, 이온주입으로 콘택트 도핑 후 비트라인(11)을 형성함을 특징으로 하는 스택 커패시터 셀의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900006472A 1990-05-08 1990-05-08 반도체 장치의 제조방법 KR920008294B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019900006472A KR920008294B1 (ko) 1990-05-08 1990-05-08 반도체 장치의 제조방법
GB9109684A GB2243951B (en) 1990-05-08 1991-05-03 A method for fabricating semiconductor devices
DE4114917A DE4114917A1 (de) 1990-05-08 1991-05-07 Verfahren zum herstellen eines halbleiterbauelements
JP3102593A JPH0719849B2 (ja) 1990-05-08 1991-05-08 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900006472A KR920008294B1 (ko) 1990-05-08 1990-05-08 반도체 장치의 제조방법

Publications (2)

Publication Number Publication Date
KR910020942A true KR910020942A (ko) 1991-12-20
KR920008294B1 KR920008294B1 (ko) 1992-09-26

Family

ID=19298780

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900006472A KR920008294B1 (ko) 1990-05-08 1990-05-08 반도체 장치의 제조방법

Country Status (4)

Country Link
JP (1) JPH0719849B2 (ko)
KR (1) KR920008294B1 (ko)
DE (1) DE4114917A1 (ko)
GB (1) GB2243951B (ko)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960004079B1 (en) * 1992-12-19 1996-03-26 Lg Semicon Co Ltd Contact hole forming method
EP0749156B1 (de) * 1995-05-23 1999-08-11 Siemens Aktiengesellschaft Halbleiteranordnung mit selbstjustierten Kontakten und Verfahren zu ihrer Herstellung

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61183952A (ja) * 1985-02-09 1986-08-16 Fujitsu Ltd 半導体記憶装置及びその製造方法
ATE97259T1 (de) * 1986-10-16 1993-11-15 Siemens Ag Speicherzellenanordnung fuer dynamische halbleiterspeicher.
JPH01129440A (ja) * 1987-11-14 1989-05-22 Fujitsu Ltd 半導体装置
JP2682021B2 (ja) * 1988-06-29 1997-11-26 富士通株式会社 半導体メモリ装置
JPH0279462A (ja) * 1988-09-14 1990-03-20 Toshiba Corp 半導体記憶装置

Also Published As

Publication number Publication date
KR920008294B1 (ko) 1992-09-26
JPH0719849B2 (ja) 1995-03-06
GB9109684D0 (en) 1991-06-26
JPH05343635A (ja) 1993-12-24
DE4114917A1 (de) 1991-11-21
GB2243951B (en) 1994-03-02
GB2243951A (en) 1991-11-13

Similar Documents

Publication Publication Date Title
JPH0465548B2 (ko)
KR900001045A (ko) 스택 커패시터 dram 셀 및 그의 제조방법
TW345752B (en) Method of manufacturing capacitor in semiconductor memory device
KR910001762A (ko) 디램셀의 제조방법
KR910020942A (ko) 스택 커패시터 셀의 제조방법
KR920015539A (ko) 싱글 폴리 이이피롬 셀 및 그 제조방법
KR920015566A (ko) 메모리 셀 제조방법
KR910017642A (ko) 스택 커패시터 셀 제조방법
KR920008934A (ko) 반도체 메모리 셀 제조방법
KR930015005A (ko) 디램셀의 제조방법
KR920015536A (ko) 디램셀의 스택커패시터 제조방법
KR920007243A (ko) 실린더형 스택 커패시터 셀 제조방법
KR930009088A (ko) 반도체 메모리장치의 커패시터 제조방법 및 커패시터 구조
KR920015573A (ko) 메모리 셀 제조방법
KR910019213A (ko) 디램의 스택 트렌치 커패시터 셀의 제조방법
KR920010819A (ko) 홀 구조를 갖는 스택 메모리 셀
KR900017148A (ko) 고집적 트렌치형 디램 셀의 제조방법
KR920005389A (ko) 디스포저블 게이트 측벽 커패시터 셀 제조방법
KR960026868A (ko) 반도체 메모리 장치의 커패시터 형성방법
KR910010749A (ko) 스택 캐패시터 및 그 제조방법
KR960016481B1 (en) Method for manufacturing a memory cell
KR910020914A (ko) 초고집적 스택형 디램셀의 제조방법
KR970030853A (ko) 불휘발성 메모리장치의 제조방법
KR960002786A (ko) 반도체 소자의 커패시터 제조방법
KR920015596A (ko) 스택 커패시터 제조방법

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20020820

Year of fee payment: 11

LAPS Lapse due to unpaid annual fee